Synopsys, Inc.

Jean-Marc Albert Forey

Kai Yang

Namit Gupta

Mahantesh D Narwade

Kuo-Ching Lin

Horia A Toma

Michael Lyons

Tien-Chun Wei

Methods and apparatuses related to clock-domain-crossing (CDC) specific design mutations to model silicon behavior and measure verification robustness are described. CDC signal paths can be identified in a circuit design. Next, synchronization circuitry associated with the CDC signal paths can be identified. Design mutations can be added to the identified synchronization circuitry. The design mutations can then be used during functional verification to measure verification robustness of a circuit verification test suite.

Clock-domain-crossing specific design mutations to model silicon behavior and measure verification robustness

Ranking of fault-test pairs is performed using first and second multitudes of waveform statistics. The first multitude of waveform statistics includes first value-change information regarding variations in logics HIGH and LOW for each bit of each reference output resulting from a test run of the design code. The second multitude of waveform statistics includes second value-change information regarding variations in logics HIGH and LOW for each bit of each faulty output resulting from a test run of the design code injected with a fault. Relative differences between the first and second multitudes of waveform statistics for each bit of each faulty output with respect to the corresponding reference output are determined. A waveform difference based on the relative differences for each signal of each faulty output is determined. A ranking result of fault-test pairs is determined according to the waveform differences of the faulty outputs.

Method for ranking fault-test pairs based on waveform statistics in a mutation-based test program evaluation system

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Grenoble, France

Jean-Marc Albert Forey