Kla Tencor Corporation

Kla-tencor Technologies Corporation

Other

Kla Corporation

Jaydeep K Sinha

Pradeep Vukkadala

Haiguang Chen

Sathish Veeraraghavan

Sergey Kamensky

Michael D Kirk

Amir Azordegan

Craig MacNaughton

Shouhong Tang

Bin-Ming Benjamin Tsai

Stephen Biellak

Oreste Donzella

Krishna Rao

Wei Chang

Enrique Chavez

Rabi Fettig

Mehdi Vaez-Iravani

George J Kren

Roy E Mallory

Andrew Zeng

Kurt Lindsay Haller

Prasanna Dighe

Joseph Gutierrez

Ramon Olavarria

Chris Koliopoulos

Ali Salehpour

Jiayao Zhang

Noel Poduje

Jong-Hoon Kim

Mark Plemmons

Soham Dey

Craig Macnaughton

John Hager

Stephen MacLeod

Delvin A Lindley

John F Valley

Systems and methods for prediction and measurement of overlay errors are disclosed. Process-induced overlay errors may be predicted or measured utilizing film force based computational mechanics models. More specifically, information with respect to the distribution of film force is provided to a finite element (FE) model to provide more accurate point-by-point predictions in cases where complex stress patterns are present. Enhanced prediction and measurement of wafer geometry induced overlay errors are also disclosed.

Process-induced distortion prediction and feedforward and feedback correction of overlay errors

Prediction based systems and methods for optimizing wafer chucking and lithography control are disclosed. Distortions predicted to occur when a wafer is chucked by a chucking device are calculated and are utilized to control chucking parameters of the chucking device. Chucking parameters may include chucking pressures and chucking sequences. In addition, predicted distortions may also be utilized to facilitate application of anticipatory corrections. Controlling chucking parameters and/or applying anticipatory corrections help reducing or minimizing overlay errors.

Prediction based chucking and lithography control optimization

Wafer geometry measurement tools and methods for providing improved wafer geometry measurements are disclosed. Wafer front side, backside and flatness measurements are taken into consideration for semiconductor process control. The measurement tools and methods in accordance with embodiments of the present disclosure are suitable for handling any types of wafers, including patterned wafers, without the shortcomings of conventional metrology systems.

Patterned wafer geometry measurements for semiconductor process controls

Systems and methods for improving results of wafer higher order shape (HOS) characterization and wafer classification are disclosed. The systems and methods in accordance with the present disclosure are based on localized shapes. A wafer map is partitioned into a plurality of measurement sites to improve the completeness of wafer shape representation. Various site based HOS metric values may be calculated for wafer characterization and/or classification purposes, and may also be utilized as control input for a downstream application. In addition, polar grid partitioning schemes are provided. Such polar grid partitioning schemes may be utilized to partition a wafer surface into measurement sites having uniform site areas while providing good wafer edge region coverage.

Systems, methods and metrics for wafer high order shape characterization and wafer classification using wafer dimensional geometry tool

Systems and methods for processing phase maps acquired using interferometer wafer geometry tools are disclosed. More specifically, instead of performing phase unwrapping first and then analyze the unwrapped data in a height domain, systems and methods in accordance with the present disclosure operate in a curvature domain without having to perform any phase unwrapping.

Systems and methods for wafer structure uniformity monitoring using interferometry wafer geometry tool

Systems and methods for providing micro defect inspection capabilities for optical systems such as wafer metrology tools and interferometer systems are disclosed. The systems and methods in accordance with the present disclosure may detect, classify and quantify wafer surface features, wherein the detected defects are classified and the important defect metrology information of height/depth, area and volume is reported. The systems and methods in accordance with the present disclosure therefore provide more values for quantifying the negative effect of these defects on the wafer quality.

Systems and methods for wafer surface feature detection, classification and quantification with wafer geometry metrology tools

The present invention may include acquiring a wafer shape value at a plurality of points of a wafer surface at a first and second process level, generating a wafer shape change value at each of the points, generating a set of slope of shape change values at each of the points, calculating a set of process tool correctables utilizing the generated set of slope of shape change values, generating a set of slope shape change residuals (SSCRs) by calculating a slope of shape change residual value at each of the points utilizing the set of process tool correctables, defining a plurality of metric analysis regions distributed across the surface, and then generating one or more residual slope shape change metrics for each metric analysis region based on one or more SSCRs within each metric analysis region.

Overlay and semiconductor process control using a wafer geometry metric

Systems and methods for prediction of in-plane distortions (IPD) due to wafer shape in semiconductor wafer chucking process is disclosed. A series of Zernike basis wafer shapes process to emulate the non-linear finite element (FE) contact mechanics model based IPD prediction is utilized in accordance with one embodiment of the present disclosure. The emulated FE model based prediction process is substantially more efficient and provides accuracy comparable to the FE model based IPD prediction that utilizes full-scale 3-D wafer and chuck geometry information and requires computation intensive simulations. Furthermore, an enhanced HOS IPD/OPD prediction process based on a series of Zernike basis wafer shape images is also disclosed.

System and method to emulate finite element model based prediction of in-plane distortions due to semiconductor wafer chucking

Systems and methods for providing improved wafer geometry measurements are disclosed. A wafer geometry measurement system may utilize techniques that enable the wafer geometry measurement system to identify and reduce wafer surface errors caused by structures such as patterns on the wafers being measured. The wafer geometry measurement system may also utilize techniques that enable the wafer geometry measurement system to accurately reconstruct patterned wafer surfaces.

Systems and methods for effective pattern wafer surface measurement and analysis using interferometry tool

Systems and methods to detect, quantify, and control process-induced asymmetric signatures using patterned wafer geometry measurements are disclosed. The system may include a geometry measurement tool configured to obtain a first set of wafer geometry measurements of the wafer prior to the wafer undergoing a fabrication process and to obtain a second set of wafer geometry measurements of the wafer after the fabrication process. The system may also include a processor in communication with the geometry measurement tool. The processor may be configured to: calculate a geometry-change map based on the first set of wafer geometry measurements and the second set of wafer geometry measurements; analyze the geometry-change map to detect an asymmetric component induced to wafer geometry by the fabrication process; and estimate an asymmetric overlay error induced by the fabrication process based on the asymmetric component detected in wafer geometry.

Process-induced asymmetry detection, quantification, and control using patterned wafer geometry measurements

Predictive modeling based focus error prediction method and system are disclosed. The method includes obtaining wafer geometry measurements of a plurality of training wafers and grouping the plurality of training wafers to provide at least one training group based on relative homogeneity of wafer geometry measurements among the plurality of training wafers. For each particular training group of the at least one training group, a predictive model is develop utilizing non-linear predictive modeling. The predictive model establishes correlations between wafer geometry parameters and focus error measurements obtained for each wafer within that particular training group, and the predictive model can be utilized to provide focus error prediction for an incoming wafer belonging to that particular training group.

Predictive wafer modeling based focus error prediction using correlations of wafers

Interferometer systems and methods for providing improved defect detection and quantification are disclosed. The systems and methods in accordance with the present disclosure may detect surface defects on patterned or bare wafer surfaces and subsequently quantify them. In certain embodiments in accordance with the present disclosure, amplitude maps of the wafer surfaces are obtained and are utilized in addition/alternative to phase maps for wafer surface feature detection. Furthermore, local one-dimensional and/or two-dimensional unwrapping techniques are also disclosed and are utilized in certain embodiments in accordance with the present disclosure to provide height and depth information of the detected defects, further improving the detection capabilities of the measurement systems.

Systems and methods for wafer surface feature detection and quantification

Methods and systems for detection of selected defects in relatively noisy inspection data are provided. One method includes applying a spatial filter algorithm to inspection data acquired across an area on a substrate to determine a first portion of the inspection data that has a higher probability of being a selected type of defect than a second portion of the inspection data. The selected type of defect includes a non-point defect. The inspection data is generated by combining two or more raw inspection data corresponding to substantially the same locations on the substrate. The method also includes generating a two-dimensional map illustrating the first portion of the inspection data. The method further includes searching the two-dimensional map for an event that has spatial characteristics that approximately match spatial characteristics of the selected type of defect and determining if the event corresponds to a defect having the selected type.

Detection of selected defects in relatively noisy inspection data

Growing community of inventors

Livermore, CA, United States of America

Jaydeep K Sinha