Sandisk Technologies Inc.

Western Digital Technologies, Inc.

Jayavel Pachamuthu

Johann Alsmeier

Peter Rabkin

Masaaki Higashitani

Yao-Sheng Lee

Yingda Dong

Raghuveer S Makala

Henry Chien

Jagdish Sabde

Liang Pang

Sagar Magia

Daniel Joseph Linnen

Kirubakaran Periyannan

George Matamis

James K Kai

Tuan Duc Pham

Jiahui Yuan

Hiroyuki Kinoshita

Vinod Robert Purayath

Matthias Baenninger

Ankitkumar Babariya

Yanli Zhang

Wei Zhao

Sateesh Koka

Masanori Terahara

Cheng-Chung Chu

Dana Lee

Ching-Huang Lu

Masatoshi Nishikawa

Fumitoshi Ito

Somesh Peri

Atsushi Suyama

Marika Gunji-Yoneoka

Amul Dhirajbhai Desai

Jarrett Jun Liang

Go Shoji

Hirofumi Watatani

Jilin Xia

Rajan Paudel

Deepak Bharadwaj

Stephen Shi

Christopher John Petti

Rahul Sharangpani

Tong Zhang

Dengtao Zhao

Mohan Dunga

Masanori Tsutsumi

Tien-Chien Kuo

Deepak Raghu

Murshed Chowdhury

Satoshi Shimizu

Jin Liu

Zhenyu Lu

Jongsun Sel

Kensuke Yamaguchi

Genta Mizuno

Hiro Kinoshita

Tadashi Nakamura

Akira Matsudaira

Tomoyuki Obu

Shuji Minagawa

Katsuo Yamada

Yuki Kasai

Ming Tian

Takumi Moriyama

Tomoyasu Kakegawa

Narendhiran Cr

Junji Oh

Fabo Yu

Ramkumar Subramanian

Everett Lyons, Iv

Daewung Kang

Tsuyoshi Hada

Tomohiro Oginoe

Yasushi Dowaki

Siddharth Bhatt

Jay Dholakia

Hoang Huynh

Dat Dinh

Luckshitha Suriyasena Liyanage

Makoto Dei

Pradhyumna Ravikirthi

A non-volatile memory system performs an erase process followed by a program process to program blocks of memory cells. The erase process comprises erasing followed by erase verification. The system recovers data and records a strike for blocks that fail a read process. In response to a particular block having a strike, the system performs an odd/even compare process during the erase process for the particular blocks having the strike such that the odd/even compare process comprises determining whether a number of memory cells connected to even word lines that have a different erase verify result than memory cells connected to odd word lines is greater than a defect test threshold. The system retires blocks from further use for storing host data that fail the odd/even compare process even if the block passes erase verification.

Non-volatile memory with efficient testing

Clamped semiconductor wafers and clamped semiconductor devices include reservoirs filled with a flowable metal which hardens to allow the wafers/devices to be shipped or stored. The hardened metal may also be reflowed to a liquid to allow clamping of the semiconductor wafers together and to allow clamping of the semiconductor packages together. The flowable metal may be filled into the reservoirs as a liquid or paste. Thereafter, the flowable metal may be cooled to harden the flowable metal into a clamping member.

Clamped semiconductor wafers and semiconductor devices

When erasing multiple sub-blocks of a block, erase verify is performed for memory cells connected to even word lines to generate even results and for memory cells connected to odd word lines to generate odd results. The even results and the odd results are used to determine that the erase verify process successfully completed. For each NAND string of a first sub-block, a last even result for the NAND string is compared to a last odd result for the NAND string. Despite the determination that the first sub-block successfully completed erase verify, the erasing failed for the first sub-block because the number of NAND strings that have the last even result different than the last odd result is greater than a limit. The system determines that one or more additional sub-blocks also failed erasing based on and in response to determining that the first sub-block failed erasing.

Non-volatile memory with efficient testing during erase

A system and method for warpage detection in a CMOS bonded array includes a conductor positioned between bonded contact pads of first and second wafers. The conductor is connected to a continuity check circuit. If the continuity check circuit detects an interruption in conductivity of the conductor, such interruption is indicative of warpage in the first and/or second wafers. In one implementation, the conductor is a serpentine-shaped structure.

System and method for warpage detection in a CMOS bonded array

A non-volatile memory system erasing groups of connected memory cells separately performs erase verify for memory cells connected to even word lines to generate even results and erase verify for memory cells connected to odd word lines to generate odd results. The even results and the odd results are used to determine if the erase verify process indicates that the erasing has successful completed. In addition, for each group of connected memory cells, a last even result for the group is compared to a last odd result for the group. Even if the erase verify indicated that the erasing has successfully completed, the system may determine that the erasing failed (i.e. due to a defect) if the number of groups of connected memory cells that have the last even result different than the last odd result is greater than a limit.

Technology is disclosed for detecting latent defects in non-volatile storage systems. Prior to writing data, a stress voltage is applied to SGS transistors in a 3D memory structure. After applying the stress voltage, the Vt of the SGS transistors are tested to determine whether they meet a criterion. The criterion may be whether a Vt distribution of the SGS transistors falls within an allowed range. If the criterion is not met, then a sub-block mode may be enabled. In the sub-block mode, data is not written to memory cells in a sub-block that contains SGS transistors whose Vt does not meet the criterion. Hence, the possibility of data loss due to defective SGS transistors is avoided. However, in the sub-block mode, data is written to memory cells in a sub-block that does not contain SGS transistors whose Vt does not meet the criterion. Hence, data capacity is preserved.

Prevention of latent block fails in three-dimensional NAND

A memory controller includes, in one embodiment, a memory interface and a controller circuit. The memory interface is configured to interface with a memory interface configured to interface with a memory having a plurality of memory blocks. Each memory block has a plurality of strings. The controller circuit is configured to perform a string defect leakage check on one of the memory blocks during a first programming operation of the one memory block, determine whether the one memory block has one or more string to string shorts based on the string defect leakage check, and resolve the string to string shorts in response to determining that the one of the memory blocks has the string to string shorts.

Memory controller for resolving string to string shorts

A semiconductor device including an integrated module formed of a first semiconductor die coupled to a second semiconductor die. Each of the first and second semiconductor dies includes a number of bond pads, which are bonded to each other to form the integrated module. Each bond pad may be divided into a number of discrete pad legs. While the overall footprint of each bond pad on the first and second semiconductor dies may be the same, the bond pads on one of the dies may have a larger number of pad legs.

Semiconductor device including coupled bond pads having differing numbers of pad legs

A method including stacking a number of silicon dice such that one or more edges of the dice are in vertical alignment, where the one or more edges include a number of connection pads. The method also includes positioning a connecting wire on a substantially perpendicular axis to the one or more edges. The connecting wire includes a number of solder blocks formed thereon. The solder blocks are spaced at intervals associated with a distance between a first set of aligned connection pads on the dice. The connecting wire is positioned such that the solder blocks are in contact with the first set of aligned connection pads. The method also includes applying heat to cause the solder blocks to reflow and physically and electrically couple the connecting wire to the connection pads.

Straight wirebonding of silicon dies

A system and method for die crack detection in a CMOS bonded array includes a capacitor that is formed in an edge seal, where one of the capacitor plates is in the edge seal portion of a first wafer, and the other capacitor plate is in the edge seal portion of a second wafer. A crack in the die can be detected by applying an alternating current waveform to a testing contact on the integrated circuit and monitoring for a shift in the alternating current waveform, as a crack would cause modulation in the capacitance.

System and method for die crack detection in a CMOS bonded array

The present technology relates to a semiconductor device including semiconductor dies formed with vertical die bond pads on an edge of the dies. During wafer fabrication, vertical bond pad blocks are formed in scribe lines of the wafer and electrically coupled to the die bond pads of the semiconductor dies. The vertical bond pad blocks are cut through during wafer dicing, thereby leaving large, vertically oriented pads exposed on a vertical edge of each semiconductor die.

Semiconductor device including vertical bond pads

A fractured semiconductor die is disclosed, together with a semiconductor device including the fractured semiconductor die. During fabrication of the semiconductor dies in a wafer, the wafer may be scored in a series of parallel scribe lines through portions of each row of semiconductor dies. The scribe lines then propagate through the full thickness of the wafer to fracture off a portion of each of the semiconductor dies. It may happen that electrical traces such as bit lines in the memory cell arrays short together during the die fracture process. These electrical shorts may be cleared by running a current through each of the electrical traces.

Semiconductor device including fractured semiconductor dies

A three-dimensional memory device includes an alternating stack of insulating layers and electrically conductive layers located over a substrate, and memory stack structures extending through the alternating stack. Each of the memory stack structures comprises a memory film and a vertical semiconductor channel contacting an inner sidewall of the memory film. The electrically conductive layers include aluminum and silicon and provide low resistance electrically conductive paths as word lines of the three-dimensional memory device. The aluminum-based electrically conductive layers can provide low resistivity, low mechanical stress, and thermal stability for use as high performance word lines.

Three-dimensional memory device containing aluminum-silicon word lines and methods of manufacturing the same

Techniques for reducing program disturb of memory cells which are formed in a NAND string extending in a lower tier and an upper tier of a stack, the lower tier including a first plurality of memory cells and the upper tier including a second plurality of memory cells, wherein each memory cell of the first and second pluralities of memory cells is connected to a respective word line. The NAND string includes a joint region formed of a dielectric material and disposed between the lower tier and the upper tier of the stack; a first non-data memory cell adjacent to and below the joint region; a second non-data memory cell adjacent to and above the joint region; and a conductive gate connected to the first non-data memory cell and the second non-data memory cell.

Program disturb improvements in multi-tier memory devices including improved non-data conductive gate implementation

Growing community of inventors

San Jose, CA, United States of America

Jayavel Pachamuthu