International Business Machines Corporation

Infineon Technologies Ag

Jay William Strane

Ruilong Xie

Hemanth Jagannathan

Carl John Radens

Yi Song

Lawrence Alfred Clevenger

Michael Rizzolo

Benjamin David Briggs

Christian Lavoie

Renee Tong Mo

Richard Anthony Conti

Mahadevaiyer Krishnan

Randolph F Knarr

Kangguo Cheng

Heng Wu

Ekmini Anuja De Silva

Eric R Miller

Christopher Joseph Waskiewicz

David M Dobuzinsky

Hiroyuki Akatsu

Veeraraghavan S Baskar

Devendra K Sadana

Bruce Bennett Doris

Anthony K Stamper

Brent A Anderson

Peng Xu

Dechao Guo

Balasubramanian Pranatharthiharan

Cyril Cabral, Jr

Fee Li Lie

Su Chen Fan

Michael P Belyansky

Sunfei Fang

Mahender Kumar

Balasubramanian S Pranatharthi Haran

Roy Charles Iggulden

Horatio Seymour Wildman

Michael A Cobb

Asa Frye

Andrew P Mansson

Huilong Zhu

Effendi Leobandung

Junli Wang

Chanro Park

Ramachandra Divakaruni

Julien Frougier

Robert Russell Robison

Min Gyu Sung

Brian Joseph Greene

Albert Manhee Chu

Johnathan E Faltermeier

Byeong Yeol Kim

Lan Yu

Rama Divakaruni

Shahab Siddiqui

Gregory Gower Freeman

Tao Li

Deok-kee Kim

Werner Robl

Matthew S Angyal

Sameer Hemchand Jain

Xiaomeng Chen

Thomas Goebel

Eric Miller

Michael Maldei

Bachir Dirahoui

Padraic C Shafer

Donna Diane Miura

Keith K H Wong

Michael M Iwatake

Brian Peter Hughes

George Worth

Curtis S Durfee

Kwong Hon (Keith) Wong

Chet Dziobkowski

Embodiments of present invention provide a semiconductor structure. The semiconductor structure includes a stack of transistors with a first transistor on top of a second transistor, where a gate of the first transistor has a first width; a gate of the second transistor has a second width; and the first width is narrower than the second width, and where the first and the second transistor respectively have a first gate extension at a first side of the stack and a second gate extension at a second side of the stack, the first gate extension at the first side of the stack being narrower than the second gate extension at the second side of the stack, with the first side being opposite the second side. A method of manufacturing the semiconductor structure is also provided.

Asymmetric gate extension in stacked FET

VFET devices having a robust gate extension structure using late gate extension patterning and self-aligned gate and source/drain region contacts are provided. In one aspect, a VFET device includes: at least one bottom source/drain region present on a substrate; at least one fin disposed on the at least one bottom source/drain region, wherein the at least one fin serves as a vertical fin channel of the VFET device; a gate stack alongside the at least one fin; a gate extension metal adjacent to the gate stack at a base of the at least one fin; a barrier layer that separates the gate extension metal from the gate stack; and at least one top source/drain region at a top of the at least one fin. A VFET device that includes multiple VFETs present on a substrate, and a method of forming a VFET device are also provided.

Late gate extension

A method includes forming a p-type field effect transistor region and an n-type field effect transistor region into a semiconductor substrate. The method implements a process flow to fabricate highly doped top source/drains with minimal lithography and etching processes. The method permits the formation of VFETs with increased functionality and reduced scaling.

CMOS top source/drain region doping and epitaxial growth for a vertical field effect transistor

A self-aligned C-shaped vertical field effect transistor includes a semiconductor substrate having an uppermost surface and a fin structure on the uppermost surface of the semiconductor substrate. The fin structure has two adjacent vertical segments with rounded ends that extend perpendicularly from the uppermost surface of the semiconductor substrate and a horizontal segment that extends between and connects the two adjacent vertical segments. An opening is located between the two adjacent vertical segments on a side of the fin structure opposite to the horizontal segment.

Self-aligned C-shaped vertical field effect transistor

Provided is a stacked field-effect transistor (FET). The stacked FET comprises a top device, a bottom device, and a transition region between the top device and the bottom device. The transition region includes a plurality of inner spacers and a first inter-layer dielectric (ILD). The ILD is formed between each of the plurality of inner spacers. The top and bottom devices have a first channel sheet thickness in a gate region and a second channel sheet thickness between inner spacers. The second channel sheet thickness is larger than both the first channel sheet thickness and the first distance.

Stacked field-effect transistors

Semiconductor devices and methods of forming the same include forming a bottom source/drain structure around a fin. A multi-layer bottom spacer is formed on the bottom source/drain structure, around the fin. Each layer of the multi-layer bottom spacer has a respective vertical height above the bottom source/drain structure, with a layer of the multi-layer bottom spacer that is farthest from the fin having a greater vertical height than a layer that is closest to the fin, to address parasitic capacitance from the bottom source/drain structure.

Self-aligned uniform bottom spacers for VTFETS

A semiconductor device includes a substrate, at least one semiconductor vertical fin extending from the substrate, a bottom source/drain region disposed beneath the at least one semiconductor vertical fin, and first and second isolation regions on respective longitudinal sides of the semiconductor vertical fin. Each of the first and second isolation regions extend vertically above the bottom source/drain region. A bottom spacer is disposed on the first and second isolation regions. A spacer segment of the bottom spacer is disposed on a first upper surface portion of the bottom source/drain region adjacent the first isolation region. A dielectric liner underlies at least portions of the first and second isolation regions. A dielectric segment of the dielectric liner is disposed on a second upper surface portion of the bottom source/drain region adjacent the second isolation region. At least one functional gate structure is disposed on the semiconductor vertical fin.

Vertical field effect transistor with bottom spacer

A method of forming a vertical channel semiconductor structure, comprises forming a source/drain layer in contact with at least one semiconductor fin. A first sacrificial layer is formed over the source/drain layer. A second sacrificial layer is formed over the first sacrificial layer. A trench is formed in the second sacrificial layer to expose a portion of the first sacrificial layer. After forming the second sacrificial layer, the first sacrificial layer is selectively removed to form a cavity under the second sacrificial layer. A spacer layer is then formed within the cavity.

Replacement bottom spacer for vertical transport field effect transistors

A finned semiconductor structure including sets of relatively wide and relatively narrow fins is obtained by employing hard masks having different quality. A relatively porous hard mask is formed over a first region of a semiconductor substrate and a relatively dense hard mask is formed over a second region of the substrate. Patterning of the different hard masks using a sidewall image transfer process causes greater lateral etching of the relatively porous hard mask than the relatively dense hard mask. A subsequent reactive ion etch to form semiconductor fins causes relatively narrow fins to be formed beneath the relatively porous hard mask and relatively wide fins to be formed beneath the relatively dense hard mask.

Dual width finned semiconductor structure

A method is presented for forming dielectric isolated fins. The method includes forming a plurality of fin structures over a semiconductor substrate, forming spacers adjacent each of the plurality of fins, recessing the semiconductor substrate to form bottom fin profiles, and forming shallow trench isolation (STI) regions between the plurality of fins and the bottom fin profiles. The method further includes etching the STI regions, a select number of the plurality of fins, and a portion of a select number of the bottom fin profiles to create cavities between a mechanical anchor defined between a pair of fins of the plurality of fins, the etching resulting in undercutting of remaining fins.

Semiconductor fins with dielectric isolation at fin bottom

Semiconductor devices and methods are provided to fabricate fin field-effect transistor (FinFET) devices having uniform fin height profiles. For example, uniformity of fin height profiles for FinFET devices is obtained by implementing a gate oxide removal process which is designed to prevent etching of an isolation layer (e.g., a shallow trench isolation layer) formed of an oxide material during removal of, e.g., sacrificial gate oxide layers of dummy gate structures during a replacement metal gate process.

Controlling active fin height of FinFET device

Controlling active fin height of FinFET device using etch protection layer to prevent recess of isolation layer during gate oxide removal

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Warwick, NY, United States of America

Jay William Strane