Intel Corporation

Asset Intertech, Inc.

Jay Joseph Nejedlo

Bruce Querbach

David G Ellis

Theodore Zale Schoenborn

Sean R Babcock

James Ernest Chorn

Thomas Green Hudiburgh

Edward Keith Simpson

Mohan J Kumar

David W Grawrock

Rahul Khanna

Christopher P Mozak

David Zimmerman

Andrew W Martwick

Zvika Greenfield

Tieyu Zheng

Keshavan K Tiruvallur

Mark B Trobough

Chinna B Prudvi

Vui Yong Liew

Hermann Gartler

Bryan L Spry

Ashok N Kabadi

Samie B Samaan

Keith A Drescher

Mukesh Kataria

Richard J Glass

Lyle E Cool

James J Grealish

Russell J Wunderlich

Philip Abraham

Abhijit Davare

Brian Meyer

Christopher E Yunker

Priyadarsan Patra

Eric S Gayles

Ridvan A Sahan

Rahima K Mohammed

Amjad M Khan

William Penner

John L Baudrexl

Jayasekhar Tholiyil

Kapila B Udawatta

Arun R Ramadorai

Wee Hoo Cheah

Yuen Tat Lee

Loren James McConnell

Kyle Markley

Rony Ghattas

Christian E Iovin

Kip C Killpack

Eshwar Gollapudi

Neil Dobler

Nagib Z Hakim

Timothy S Storey

Yi Amy Xia

Edwin E Parks

Padmakumar Gopal

Sanjay S Salem

David C Florey

Charles D Lucas

Travis K Goff

Evan J Halprin

Jiun Long Foo

Walter Michael Coldewey

Selvakumar Raja Gopal

Mike Wiznerowicz

An apparatus and method is described herein for providing a test, validation, and debug architecture. At a target or base level, hardware hooks (Design for Test or DFx) are designed into and integrated with silicon parts. A controller may provide abstracted access to such hooks, such as through an abstraction layer that abstracts low level details of the hardware DFx. In addition, the abstraction layer through an interface, such as APIs, provides services, routines, and data structures to higher-level software/presentation layers, which are able to collect test data for validation and debug of a unit/platform under test. Moreover, the architecture potentially provides tiered (multiple levels of) secure access to the test architecture. Additionally, physical access to the test architecture for a platform may be simplified through use of a unified, bi-directional test access port, while also potentially allowing remote access to perform remote test and debug of a part/platform under test. In essence, a complete test architecture stack is described herein for test, validation, and debug of electronic parts, devices, and platforms.

Test, validation, and debug architecture

REUT (Robust Electrical Unified Testing) for memory links is introduced which speeds testing, tool development, and debug. In addition it provides training hooks that have enough performance to be used by BIOS to train parameters and conditions that have not been possible with past implementations. Address pattern generation circuitry is also disclosed.

Robust memory link testing using memory controller

A graphical user interface (GUI) that configures a test for a circuit. More particularly, the circuit includes a built-in-self-test (BIST) compatible device and has a test configuration. The device has an associated value. Moreover, the circuit, the device, and the associated value are defined in a circuit definition. The GUI includes a GUI object representing the circuit, a GUI object representing the BIST compatible device, and a GUI object representing the associated value. Furthermore, at least one of the GUI objects is configured to allow a modification to the GUI object and to reconfigure the test configuration in response to the GUI object modification. Also, the GUI object is further configured to modify itself to reflect a modification of the circuit definition. More particularly, the device may be an interconnect built-in self-test (IBIST) compatible device having registers, ports and lanes of the ports.

Graphical user interface for creation of IBIST tests

Methods and apparatus for performing a data driven test on a circuit including at least one built-in-self-test compatible device. In one embodiment, the method includes describing the device using a descriptive language including setting at least one default value associated with the device. The method also includes defining a scan path associated with the device, defining a netlist of the circuit, and configuring a test control program for the circuit. Additionally, the method includes changing the default value associated with the device. Testing the circuit after changing the value and using the test control program is also included wherein a portion of the test control program associated with the value remains substantially unmodified.

User data driven test control software application the requires no software maintenance

In some embodiments, built-in self-test logic is provided for an integrated circuit (IC) device having memory controller logic to generate address and command information for accessing a memory device. Driver circuits are on-chip with the memory controller logic. The driver circuits have outputs that are coupled to on-chip signal pads, respectively. The BIST logic is coupled between the driver circuits and the controller logic. The BIST logic is to transmit, at speed, address and command information that has been generated by the controller logic using the driver circuits in a normal mode of operation for the device. In addition, the BIST logic is able to transmit, at speed, test symbols using the driver circuits in a test mode of operation for the IC device, during which a chip-to-chip connection between the IC device and another device is tested. Other embodiments are also described and claimed.

Built-in self test for memory interconnect testing

According to one embodiment, a built-in self test (IBIST) architecture/methodology is disclosed. The IBIST provides for testing the functionality of an interconnect (such as a bus) between a transmitter and a receiver component. The IBIST architecture includes a pattern generator and a pattern checker. The pattern checker operates to compare a received plurality of bits (for the pattern generator) with a previously stored plurality of bits.

High performance serial bus testing methodology

Training of a link is performed, wherein the link is an interconnect between two devices of a computer system. A built-in self-test (BIST) of the link is performed. A result from the link training is compared to a result from the BIST. A link status of the link is posted, wherein the link status is based at least in part on the result from the link training and the result from the BIST.

Automated BIST execution scheme for a link

A methodology for testing a computer system using multiple test units, each test unit being associated with its respective core function circuitry. The core circuitry and its respective test unit are located in a primary integrated circuit component of the computer system, such as a processor, memory, or chipset. The on-chip test units communicate with one another and with other parts of the system, to determine whether a specification of the computer system is satisfied, without requiring a processor core of the computer system to execute an operating system program for the computer system.

Reusable, built-in self-test methodology for computer systems

A built-in self test (IBIST) architecture/methodology is provided for testing the functionality of an interconnect (such as a bus) between two components. This IBIST architecture may include a pattern generator and a pattern checker. The pattern checker operates to compare a received plurality of bits (for the pattern generator) with a previously stored plurality of bits.

Testing methodology and apparatus for interconnects

A built-in self test (BIST) unit, of a primary integrated circuit (IC) component of a computer system, is programmed or hardwired with a test pattern. The test pattern is launched in multiple test cycles, to test an interconnect bus of the computer system or perform a device validation test of the component. A pin assignment of the pattern is automatically changed after each test cycle, without requiring re-programming of the BIST unit to do so.

Push button mode automatic pattern switching for interconnect built-in self test

Growing community of inventors

Wilsonville, OR, United States of America

Jay Joseph Nejedlo