Semiconductor Components Industries, LLC

Jay A Yoder

Stephen St Germain

James Price Letterman, Jr

Joseph K Fauty

Dennis Lee Conner

Francis J Carney

Phillip Celaya

William F Burghout

Michael John Seddon

Gordon M Grivna

Roger Arbuthnot

Andrew Celaya

Frank Robert Cervantes

James H Knapp

Harold Anderson

Methods of forming semiconductor packages include providing a lead frame having leads and no tie-bars. Tape is attached to the lead frame and one or more semiconductor die are coupled therewith. Electrical contacts of the die are interconnected with the leads using electrical connectors. An encapsulated assembly is formed by at least partially encapsulating the die and electrical connectors. The assembly is singulated to form a semiconductor package. The tape is detached from the package or encapsulated assembly. One or more die attach flags may be attached to the tape and the die may be attached thereto. Semiconductor packages formed using the methods include one or more semiconductor die at least partially encapsulated, pins exposed through the encapsulant, electrical connectors within the encapsulant and electrically interconnecting the pins with electrical contacts of the die, and no tie-bars coupling the die with the pins. Packages may also include die attach flags.

Semiconductor package structures and methods of manufacture

Implementations of a semiconductor device package may include: a plurality of electrical contacts on a first face of a die, at least one clip electrically and mechanically coupled with at least one electrical contact on a second face of the die where the second face of the die is on an opposing side of the die from the first face of the die. The at least one clip may include at least one lead in electrical communication with the at least one electrical contact on the second face of the die. A mold compound or an encapsulating compound may be included around the die and a majority of the at least one clip where a portion of the at least one lead and a portion of the plurality of electrical contacts on the first face of the die are not overmolded or encapsulated. The semiconductor package includes no lead frame.

Single or multi chip module package and related methods

A system, in some embodiments, comprises: a first surface of a lead frame; a second surface of the lead frame, opposite the first surface, said second surface having been etched; and one or more holes passing through said lead frame and coincident with the first and second surfaces, wherein said one or more holes are adapted to control fluid flow on said first surface.

Holes and dimples to control solder flow

In one embodiment, semiconductor die are singulated from a semiconductor wafer having a layer of material by placing the semiconductor wafer onto a carrier tape with the layer of material adjacent the carrier tape, forming singulation lines through the semiconductor wafer to expose the layer of material within the singulation lines, and separating portions of the layer of material using a fluid.

Semiconductor die singulation method

A method of forming a semiconductor device package. Implementations may include providing an adhesive tape; contacting at least one electrical contact of at least one die with an adhesive surface of the adhesive tape; mechanically and electrically coupling at least one clip with the at least one die and contacting an electrical contact of the at least one clip with the adhesive surface; one of overmolding and encapsulating the at least one die and a majority of the at least one clip with one of a mold compound and an encapsulating compound, respectively, wherein the at least one electrical contact of the at least one die and the electrical contact of the at least one clip are not one of overmolded and encapsulated, forming the semiconductor device package; removing the semiconductor device package from the adhesive surface; and including no leadframe in the package.

In one embodiment, semiconductor die are singulated from a semiconductor wafer having a backmetal layer by placing the semiconductor wafer onto a carrier tape with the backmetal layer adjacent the carrier tape, forming singulation lines through the semiconductor wafer to expose the backmetal layer within the singulation lines, and separating portions of the backmetal layer using a fluid.

In one embodiment, semiconductor die are singulated from a semiconductor wafer having a backmetal layer by placing the semiconductor wafer onto a carrier tape with the backmetal layer adjacent the carrier tape, forming singulation lines through the semiconductor wafer to expose the backmetal layer within the singulation lines, and separating portions of the backmetal layer within the singulation lines using a pressurized fluid applied to the carrier tape.

In one embodiment, semiconductor die are singulated from a semiconductor wafer having a backmetal layer by placing the semiconductor wafer onto a carrier tape with the backmetal layer adjacent the carrier tape, forming singulation lines through the semiconductor wafer to expose the backmetal layer within the singulation lines, and fluid machining the semiconductor wafer to remove the backmetal layer from the singulation lines.

A semiconductor device () is made by mounting the bottom surfaces () of a semiconductor die () and a lead () on a tape () and over a hole () in the tape. A vacuum is drawn through the hole to secure the die in place when the lead's top surface () is wirebonded to a top surface () of the semiconductor die. A molding material () is formed to encapsulate the top surface of the semiconductor die and to expose its bottom surface.

Method of marking a low profile packaged semiconductor device

In one embodiment, a leadless package includes down-set conductive leads having base portions. The base portions include stand-offs that attach to electrodes on an electronic chip using, for example, a solder die attach material. An optional encapsulating layer covers portions of the down-set conductive leads and portions of the electronic chip while leaving pad portions of the down-set conductive leads and a surface of the electronic chip exposed. The pad portions and the surface of the electronic chip are oriented to attach to a next level of assembly.

Electronic package having down-set leads and method

In one exemplary embodiment, a multi-chip connector is formed to have a first conductive strip that is suitable for attaching to a first semiconductor die and a second conductive strip that is attached suitable for attaching to a second semiconductor die.

Growing community of inventors

Phoenix, AZ, United States of America

Jay A Yoder