Adeia Semiconductor Bonding Technologies Inc.

Adeia Semiconductor Inc.

Adeia Semiconductor Technologies LLC

Invensas Bonding Technologies, Inc.

Invensas LLC

Javier A DeLaCruz

Belgacem Haba

Ilyas Mohammed

Rajesh Katkar

Steven L Teig

Shaowu Huang

Liang Wang

David Edward Fisch

Kenneth Duong

Arkalgud R Sitaram

Gaius Gillman Fountain, Jr

Eric Nequist

William C Plants

Paul M Enquist

Jung Ko

Cyprian Emeka Uzoh

Guilian Gao

Laura Wills Mirkarimi

Don Draper

Gabriel Z Guevara

Stephen L Morein

Pearl Po-Yee Cheng

Richard E Perego

Craig S Mitchell

Ashok S Prabhu

Zhuowen Sun

Akash Agrawal

Abiola A Awujoola

Christopher Lattin

Sangil Lee

Xu Chang

Guy Regev

Wael Zohni

Min Tao

Thomas Workman

Hoki Kim

Laura Willis Mirkarimi

David E Fisch

Jr Gaius Gillman Fountain

Embedded organic interposers for high bandwidth are provided. Example embedded organic interposers provide thick conductors with more dielectric space, and more routing layers of such conductors than conventional interposers, in order to provide high bandwidth transmission capacity over longer spans. The embedded organic interposers provide high bandwidth transmission paths between components such as HBM, HBM2, and HBM3 memory stacks, and other components. To provide the thick conductors and more routing layers for greater transmission capacity, extra space is achieved by embedding the organic interposers in the core of the package. Example embedded organic interposers lower a resistive-capacitive (RC) load of the routing layers to provide an improved data transfer rate of 1 gigabits per second over at least a 6 mm span, for example. The embedded interposers are not limited to use with memory modules.

Embedded organic interposer for high bandwidth

A bonded structure is disclosed. The bonded structure can include a semiconductor element comprising active circuitry and a first bonding layer. The bonded structure can include a protective element directly bonded to the semiconductor element without an adhesive along a bonding interface. The protective element can include an obstructive material disposed over the active circuitry and a second bonding layer on the obstructive material. The second bonding layer can be directly bonded to the first bonding layer without an adhesive. The obstructive material can be configured to obstruct external access to the active circuitry.

Bonded structure including an obstructive element directly bonded to a semiconductor element without an adhesive

A bonded structure is disclosed. The bonded structure can include a semiconductor element comprising active circuitry. The bonded structure can include a protective element directly bonded to the semiconductor element without an adhesive along a bonding interface. The protective element can include an obstructive material disposed over at least a portion of the active circuitry. The obstructive material can be configured to obstruct external access to the active circuitry. The bonded structure can include a disruption structure configured to disrupt functionality of the at least a portion of the active circuitry upon debonding of the protective element from the semiconductor element.

Protective elements for bonded structures

A bonded structure is disclosed. The bonded structure can include a first element that has a first plurality of contact pads. The first plurality of contact pads includes a first contact pad and a second redundant contact pad. The bonded structure can also include a second element directly bonded to the first element without an intervening adhesive. The second element has a second plurality of contact pads. The second plurality of contact pads includes a third contact pad and a fourth redundant contact pad. The first contact pad is configured to connect to the third contact pad. The second contact pad is configured to connect to the fourth contact pad. The bonded structure can include circuitry that has a first state in which an electrical signal is transferred to the first contact pad and a second state in which the electrical signal is transferred to the second contact pad.

Circuitry for electrical redundancy in bonded structures

Direct-bonded native interconnects and active base dies are provided. In a microelectronic architecture, active dies or chiplets connect to an active base die via their core-level conductors. These native interconnects provide short data paths, which forgo the overhead of standard interfaces. The system saves redistribution routing as the native interconnects couple in place. The base die may contain custom logic, allowing the attached dies to provide stock functions. The architecture can connect diverse interconnect types and chiplets from various process nodes, operating at different voltages. The base die may have state elements for drive. Functional blocks aboard the base die receive native signals from diverse chiplets, and communicate with all attached chiplets. The chiplets may share processing and memory resources of the base die. Routing blockages are minimal, improving signal quality and timing. The system can operate at dual or quad data rates. The architecture facilitates ASIC, ASSP, and FPGA ICs and neural networks, reducing footprint and power requirements.

Direct-bonded native interconnects and active base die

Some embodiments of the invention provide a three-dimensional (3D) circuit that is formed by stacking two or more integrated circuit (IC) dies to at least partially overlap and to share one or more interconnect layers that distribute power, clock and/or data-bus signals. The shared interconnect layers include interconnect segments that carry power, clock and/or data-bus signals. In some embodiments, the shared interconnect layers are higher level interconnect layers (e.g., the top interconnect layer of each IC die). In some embodiments, the stacked IC dies of the 3D circuit include first and second IC dies. The first die includes a first semiconductor substrate and a first set of interconnect layers defined above the first semiconductor substrate. Similarly, the second IC die includes a second semiconductor substrate and a second set of interconnect layers defined above the second semiconductor substrate. As further described below, the first and second dies in some embodiments are placed in a face-to-face arrangement (e.g., a vertically stacked arrangement) that has the first and second set of interconnect layers facing each other. In some embodiments, a subset of one or more interconnect layers of the second set interconnect layers of the second die has interconnect wiring that carries power, clock and/or data-bus signals that are supplied to the first IC die.

3D chip sharing data bus

Some embodiments provide a three-dimensional (3D) circuit that has data lines of one or more memory circuits on a different IC die than the IC die(s) on which the memory blocks of the memory circuit(s) are defined. In some embodiments, the 3D circuit includes a first IC die with a first set of two or more memory blocks that have a first set of data lines. The 3D circuit also includes a second IC die that is stacked with the first IC dies and that includes a second set of two or more memory blocks with a second set of data lines. The 3D circuit further includes a third IC die that is stacked with the first and second IC dies and that includes a third set of data lines, which connect through several z-axis connections with the first and second sets of data lines to carry data to and from the first and second memory block sets when data is being written to and read from the first and second memory block sets. The z-axis connections in some embodiments electrically connect circuit nodes in overlapping portions of the first and third IC dies, and overlapping portions of second and third IC dies, in order to carry data between the third set of data lines on the third IC die and the first and second set of data lines of the first and second of memory block sets on the first and second IC dies. These z-axis connections between the dies are very short as the dies are very thin. For instance, in some embodiments, the z-axis connections are less than 10 or 20 microns. The z-axis connections are through silicon vias (TSVs) in some embodiments.

3D memory circuit

A memory structure is provided, including a NAND block comprising a plurality of oxide layers, the plurality of layers forming a staircase structure at a first edge of the NAND block, a plurality of vias disposed on the staircase structure of NAND block, two or more of plurality of vias terminating along a same plane, a plurality of first bonding interconnects disposed on the plurality of vias, a plurality of bitlines extending across the NAND block, and a plurality of second bonding interconnects disposed along the bitlines. The memory structure may be stacked on another of the memory structure to form a stacked memory device.

Apparatus for non-volatile random access memory stacks

The technology relates to a system on chip (SoC). The SoC may include a plurality of network layers which may assist electrical communications either horizontally or vertically among components from different device layers. In one embodiment, a system on chip (SoC) includes a plurality of network layers, each network layer including one or more routers, and more than one device layers, each of the plurality of network layers respectively bonded to one of the device layers. In another embodiment, a method for forming a system on chip (SoC) includes forming a plurality of network layers in an interconnect, wherein each network layer is bonded to an active surface of a respective device layer in a plurality of device layer.

Symbiotic network on layers

It is highly desirable in electronic systems to conserve space on printed circuit boards (PCB). This disclosure describes voltage regulation in electronic systems, and more specifically to integrating voltage regulators and associated passive components into semiconductor packages with at least a portion of the circuits whose voltage(s) they are regulating.

Integrated voltage regulator and passive components

Integrated optical waveguides, direct-bonded waveguide interface joints, optical routing and interconnects are provided. An example optical interconnect joins first and second optical conduits. A first direct oxide bond at room temperature joins outer claddings of the two optical conduits and a second direct bond joins the inner light-transmitting cores of the two conduits at an annealing temperature. The two low-temperature bonds allow photonics to coexist in an integrated circuit or microelectronics package without conventional high-temperatures detrimental to microelectronics. Direct-bonded square, rectangular, polygonal, and noncircular optical interfaces provide better matching with rectangular waveguides and better performance. Direct oxide-bonding processes can be applied to create running waveguides, photonic wires, and optical routing in an integrated circuit package or in chip-to-chip optical communications without need for conventional optical couplers. An example wafer-level process fabricates running waveguides, optical routing, and direct-bonded optical interconnects for silicon photonics and optoelectronics packages when two wafers are joined.

Integrated optical waveguides, direct-bonded waveguide interface joints, optical routing and interconnects

A microelectronic unit may include an epitaxial silicon layer having a source and a drain, a buried oxide layer beneath the epitaxial silicon layer, an ohmic contact extending through the buried oxide layer, a dielectric layer beneath the buried oxide layer, and a conductive element extending through the dielectric layer. The source and the drain may be doped portions of the epitaxial silicon layer. The ohmic contact may be coupled to a lower surface of one of the source or the drain. The conductive element may be coupled to a lower surface of the ohmic contact. A portion of the conductive element may be exposed at the second dielectric surface of the dielectric layer. The second dielectric surface may be directly bonded to an external component to form a microelectronic assembly.

Transistor level interconnection methodologies utilizing 3D interconnects

A microelectronic assembly may include a semiconductor wafer having first and second surfaces extending in first and second directions, the semiconductor wafer having network nodes connected to one another via local adjacent connections each extending in only one of the first and second directions, and an interconnection structure comprising a low-loss dielectric material and having first and second opposite surfaces extending in third and fourth directions each oriented at an oblique angle relative to the first and second directions, the interconnection structure having local oblique connections each extending in only one of the third and fourth directions. The semiconductor wafer may be directly bonded to the interconnection structure such that each of the network nodes is connected with at least one of the other network nodes, without use of conductive bonding material, through at least one of the local adjacent connections and at least one of the local oblique connections.

Scalable architecture for reduced cycles across SOC

Stacked IC structure with orthogonal interconnect layers

Growing community of inventors

San Jose, CA, United States of America

Javier A DeLaCruz