Virage Logic Corporation

Virage Locic Corp.

Jaroslav Raszka

Narbeh Derhacobian

Alexander Shubat

Vipin Kumar Tiwari

Kim-Kwong Michael Han

Richard Stephen Roy

Adam Kablanian

Rohit Pandey

Various apparatuses and methods in which a sense amplifier circuit couples to a current source to provide current for the sense amplifier circuit and also couples to one or more memory cells to sense a charge being stored by each memory cell. Store protection circuitry reduces a voltage potential across critical nodes of the sense amplifier circuit to a difference between a store voltage and Vdd when the store voltage is about to be applied to any of the one or more memory cells. The store protection circuitry connects Vdd to one or more of the critical nodes of the sense amplifier circuit when the store voltage is about to be applied to any of the one or more memory cells.

Methods and apparatuses for a sense amplifier

Various methods, apparatuses and systems in which a memory uses a noise reduction circuit to sense groups of memory cells. The memory has a plurality of memory cells organized into groups of memory cells. The noise reduction circuit performs a sense operation on a first group of memory cells at the substantially the same time. The noise reduction circuit performs a sense operation on a second group of memory cells at substantially the same time. The noise reduction circuit has timing circuitry to sense the second group of memory cells after the sense of the first group initiates but prior to the completion of the sense operation on the first group of memory cells.

Memory cell sensing with low noise generation

Various apparatuses and methods in which a dual-polarity non-volatile memory cell includes a sense mode component and a charge mode component. The sense mode component communicates information stored in the dual-polarity non-volatile memory cell during a read operation. The charge mode component facilitates storing of the information stored in the dual-polarity non-volatile memory cell. The charge mode component includes a first coupling capacitor and a second tunneling capacitor in a first well, and a first tunneling capacitor and a second coupling capacitor in a second well.

Methods and apparatuses for a dual-polarity non-volatile memory cell

A method, apparatus, and system in which an embedded memory comprises one or more electrically-alterable non-volatile memory cells that include a coupling capacitor, a read transistor, and a tunneling capacitor. The coupling capacitor has a first gate composed of both N+ doped material and P+ doped material, and a P+ doped region abutted to a N+ doped region. The P+ doped region abutted to the N+ doped region surrounds the first gate. The read transistor has a second gate. The tunneling capacitor has a third gate composed of both N+ doped material and P+ doped material.

Electrically-alterable non-volatile memory cell

Various apparatuses and methods are shown in which an integrated circuit includes a dual-polarity non-volatile memory cell and a test circuit. The test circuit has a bias voltage generator and a first switch. The bias voltage generator couples to the dual-polarity non-volatile memory cell via the first switch.

Methods and apparatuses for test circuitry for a dual-polarity non-volatile memory cell

Various apparatuses and methods in which an integrated circuit includes a non-volatile memory cell and a keep mode circuit. The non-volatile memory cell has a charge storage component. The keep mode circuit has a storage device and a keep mode switch. The storage device receives information stored in the non-volatile memory cell. The keep mode switch connects the storage device to the non-volatile memory cell in order to apply a static bias voltage across the charge storage component to restrict charge-loss to a predetermined level.

Methods and apparatuses for maintaining information stored in a non-volatile memory cell

A method, apparatus, and system in which an embedded memory comprises one or more electrically-alterable non-volatile memory cells that include a coupling capacitor, a read transistor, and a tunneling capacitor. The coupling capacitor has a first gate composed of both N&plus; doped material and P&plus; doped material, and a P&plus; doped region abutted to a N&plus; doped region. The P&plus; doped region abutted to the N&plus; doped region surrounds the first gate. The read transistor has a second gate. The tunneling capacitor has a third gate composed of both N&plus; doped material and P&plus; doped material.

Self-referenced, built-in access shutdown mechanism for a memory circuit. Instead of using a separate reference decoder/driver block and reference wordline path in the access timing loop, a wordline selected for accessing a core cell itself is utilized for referencing a shutdown sequence. A pair of complementary reference bitlines (BLS and BLE) are operable with a column of reference cells disposed in the row decoder. BLS/BLE control logic circuitry is operable to fine-tune the WL pulse width so as to minimize dead time and power consumption in access cycle operations.

Built-in precision shutdown apparatus for effectuating self-referenced access timing scheme

Circuitry and method for effectuating low power read operations in a memory circuit, e.g., a memory instance having a banked architecture. When a memory read cycle is initiated with respect to a particular memory cell in a selected bank based on a plurality of address signals, a specific wordline associated with the memory cell is driven high. Upon waiting until the bitline coupled thereto reach a predetermined sense level, the wordline is shut off based on a reference memory cell structure, which wordline thereby stops driving the bitline. Subsequently, after waiting for a select time, the sense amplifier senses the data stored in the particular memory cell based a charge distribution between its internal node(s) and the bitline after the selected wordline is deactivated.

Low power read circuitry for a memory circuit based on charge redistribution between bitlines and sense amplifier

A self-timed write control memory device minimizes the memory cycle time for the cells of the array. The self-timed write control memory device preferably comprises an X-decoder, a word-line driver, a memory cell array, control logic, pre-charge circuits, sense amplifiers, a reference decoder, and a reference word-line driver. The memory device preferably further includes a first reference cell, a second reference cell or logic, a first reference column, a second reference column and a reference sense amplifier. The first reference cell is preferably used for detection of read cycle completion and the second reference cell or logic is used for detection of write cycle completion. The output of the first reference cell and second reference cell are preferably coupled to inputs of a unique reference sense amplifier. The sense amplifier includes special circuitry that uses either the output of the first reference cell or the second reference cell to generate the self-timed clock and there by minimizes the memory cycle time. The second reference cell may be any one of a conventional memory cell or write reference logic.

Fast read/write cycle memory device having a self-timed read/write control circuit

A dual port memory device comprises a first group of bit lines corresponding to a first port of the device, a second group of bit lines corresponding to a second port of the device, and a vertical shielding layer disposed between the first group of bit lines and the second group of bit lines, for eliminating the capacitance coupling between the first group of bit lines and the second group of bit lines. The first group of bit lines are disposed in a first metal layer of the device, the vertical shielding is disposed in a second metal layer of the device, and the second group of bit lines are disposed in a third metal layer of the device. The present invention further comprises jumper lines for electrically connecting the bit lines in the metal layer above the vertical shielding layer to a diffusion well of a transistor. In addition, jumper windows are provided in the vertical shielding layer for allowing the jumper lines to pass through the vertical shielding layer.

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Fremont, CA, United States of America

Jaroslav Raszka