Texas Instruments Corporation

Semiconductor Components Industries, LLC

Intellectual Ventures II LLC

Aptina Imaging Corporation

Other

Isetex, Inc.

Crosstek Capital, LLC

Foveon, Inc.

Dalsa Corporation

Olympus Optical Company, Ltd.

Intellectual Ventures I LLC

Isetec, Inc

Jaroslav Hynecek

Hirofumi Komori

Leonard Forbes

Homayoon Haddad

Thomas Joy

Xia Zhao

Gennadiy A Agranov

Vladimir Korobov

Alan Neal Cooper

Richard B Merrill

Chung Chun Wan

Russel A Martin

Xiangli Li

Richard A Chapman

Michael A Kinch

Alexander Krymski

William P McCracken

Eric Gordon Stevens

Christopher Parks

Douglas Raymond Dykaar

Jeffery S Beck

Masao Uehara

Eric Charles Fox

Charles G Roberts

Adam J Lewis, Jr

Bartosz Piotr Banachowicz

Matthew J Fritz

Hyung-Jun Han

Russell J Austin

Stephen Kosman

Hiroaki Shibuya

Various embodiments of the present technology may comprise methods and apparatus for an image sensor capable of simultaneous integration of electrons and holes. According to an exemplary embodiment, the image sensor comprises a backside-illuminated hybrid bonded stacked chip image senor comprising a pixel circuit array, and each pixel circuit comprising a charge storage capacitor oriented in a vertical direction in a deep trench isolation region. Both the electrons and holes are integrated (collected) using a global shutter operation, and the charge storage capacitor is used for storing a signal generated by the holes.

Stacked image sensor capable of simultaneous integration of electrons and holes

A back side illuminated image sensor may operate using the single-photon avalanche diode (SPAD) concept in a Geiger mode of operation for single photon detection. The image sensor may be implemented using two layer stacking with a silicon on insulator (SOI) chip. The chip-to-chip electrical connections between the top level image sensing chip and the second level ASIC circuit chip may be realized at each pixel with a single bump connection per pixel. A light level signal may be obtained from pixels that have photon counting capabilities while a distance measurement signal for 3-dimensional imaging may be obtained from pixels that have time-of-flight (ToF) detection capabilities. Both types of pixels may be integrated within the same array and use the same SPAD structure placed on the top chip.

Single-photon avalanche diode image sensor with photon counting and time-of-flight detection capabilities

An image sensor may be provided with an array of image sensor pixels formed on a substrate having front and back surfaces. Each pixel may have a photodiode that receives light through the back surface, a floating diffusion node, a charge transfer gate, and first and second reset transistor gates. A source follower transistor may have a gate coupled to the floating diffusion node and a source coupled to an addressing transistor. The pixel may be coupled to a column feedback amplifier through the addressing transistor and a column feedback reset path. The amplifier may provide a kTC-reset noise compensation voltage to the reset transistors for storage on a holding capacitor coupled between the floating diffusion and a drain terminal of the source follower. The floating diffusion may be bounded at the front surface by the transfer gate, the reset gate, and p-type doped regions.

Global shutter image sensor pixels having improved shutter efficiency

Various embodiments of the present technology may comprise methods and apparatus for an image sensor capable of simultaneous integration of electrons and holes. According to an exemplary embodiment, the image sensor comprises a backside-illuminated hybrid bonded stacked chip image sensor comprising a pixel circuit array, and each pixel circuit comprising a charge storage capacitor oriented in a vertical direction in a deep trench isolation region. Both the electrons and holes are generated and integrated (collected) in the pixel simultaneously, and the charge storage capacitor is used for storing the signal generated by holes in the high light level illuminated pixels.

Method and apparatus for an image sensor capable of simultaneous integration of electrons and holes

Electronic devices may include High Dynamic Range (HDR) complementary metal-oxide-semiconductor (CMOS) image sensor arrays that are illuminated from the back side of the substrate and operate in a rolling shutter (RS) scanning mode. An image sensor may include stacked chips to improve image sensor performance. For example, by stacking photodiodes on top of each other and using dichroic dielectric layers in chip-to-chip isolation, sensor sensitivity may be increased, Moir&#xe9; effect may be reduced, and the overall image sensor performance may be improved. Image sensors may include a charge sensing and charge storing scheme where charge generated by low incident light levels is transferred onto a charge sensing node of an in-pixel inverting feedback amplifier and charge generated by high incident light levels overflows a certain potential barrier built in the pixel, is stored on capacitors, and is sensed by a source follower.

Image sensors with stacked photodiodes

An image sensor may include an array of image sensor pixels. Each pixel may have a photodiode, a floating diffusion node, and a charge transferring transistor. The charge transferring transistor may be a dual gate transistor having first and second gate terminals. A suitable bias may be applied to the second gate terminal to alter the capacitance of the floating diffusion node. The amount of electrons that may be accommodated by the floating diffusion node may be altered with application of a varying voltage level bias at the second gate terminal. By implementing a dual gate transistor, dynamic range compression and anti-blooming charge overflow may be implemented directly in the pixel to reduce image sensor pixel size and cost.

Image sensor pixels having dual gate charge transferring transistors

A global shutter image sensor may include an array of image sensor pixels. Each pixel may have a photodiode, a charge storage region, low light level circuitry and high light level circuitry. During high light level conditions, some charge generated by the photodiode may be diverted to the high light level circuitry and the remainder may be transferred to the low light level circuitry. During low light level conditions, all of the generated charge may be transferred to the low light level circuitry. A light shielding structure may be formed over the charge storage region. The circuit components of each pixel may be divided between first and second chips. By forming the components on separate chips and by implementing high light level circuitry, the size of the charge storage region may be reduced while preserving the high dynamic range and low noise of the image sensor during all illumination conditions.

High dynamic range global shutter image sensors having high shutter efficiency

An image sensor may include an array of image sensor pixels. Each pixel may have a photodiode, a charge storage region, and a charge overflow circuit. The charge storage region may be used to operate the image sensor array in global shutter mode. During high light level illumination, the charge overflow circuit may divert charge away from the photodiode such that only a predetermined portion of the accumulated charge remains in the photodiode. During low light level illumination all of the accumulated charge may be stored in the pixel photodiode. The charge overflow circuit may include a transistor and a resistor or capacitor. By implementing a charge overflow circuit, the size of the charge storage region may be reduced while still preserving the high dynamic range and low noise of the image sensor during all light illumination conditions.

High dynamic range and global shutter image sensor pixels having charge overflow signal detecting structures

A backside illuminated image sensor includes a substrate, a backside passivation layer disposed on backside of the substrate, and a transparent conductive layer disposed on the backside passivation layer.

Backside illuminated image sensor

In one form, a hybrid bonded image sensor comprises a photodiode chip, a circuit carrying chip, and an interconnection. The photodiode chip provides charge to a first floating diffusion in response to incident light, wherein the first floating diffusion is coupled to a first terminal on a first surface of the photodiode chip. The circuit carrying chip has a first terminal aligned with the first terminal of the photodiode chip, the circuit carrying chip forming an output voltage based on charge transferred on the first floating diffusion sensed from the first terminal thereof. The interconnection connects the first terminal of the photodiode chip to the first terminal of the circuit carrying chip.

Hybrid bonded image sensor and method of operating such image sensor

Imaging pixels may be operated in a rolling shutter scanning mode. Charge signal that is generated on a first chip may be capacitively coupled to signal processing circuits on a second chip. A capacitor may be placed in the signal path that provides signal coupling between the chips and stores overflow charge from pixels that have been exposed to high light level illumination. This enables high dynamic range using only a single charge integration time. The pixel may include an in-pixel negative feedback amplifier. The chip-to-chip electrical connections between the first and second chips may be realized at each pixel as a hybrid bond with a single bond per pixel. Image sensors fabricated using this technology may have small size pixels, high resolution, high dynamic range, and a single charge integration time.

Image sensors with a rolling shutter scanning mode and high dynamic range

A CMOS image sensor may have back-side illuminated pixels and operate in a global shutter scanning mode. The CMOS image sensor may be implemented using three-layer chip stacking. The chip to chip electrical connections between the upper chip and the middle chip may be formed via hybrid bonding. Two bonding pads may be included in each pixel. The electrical connections between the middle chip and the lower chip may be formed at the periphery of the array. Using three-layer chip stacking with hybrid bonding allows for the transferring and storing of signals from the upper chip on the middle chip. A signal from low light level illumination and a charge overflow signal from high light level illumination may both be transferred to the middle chip. The image sensor may be able to use a global shutter scanning mode having high dynamic range.

Pixels with high dynamic range and a global shutter scanning mode

In electron multiplying charge coupled device (EMCCD) image sensors, electron traps in the dielectric stack underneath charge multiplication electrodes may cause undesirable gain ageing. To reduce the gain ageing drift effect, a dielectric stack may be formed that does not include electron traps in regions underneath charge multiplication electrodes. To accomplish this, silicon nitride in the dielectric stack may be removed in regions underneath the charge multiplication electrodes. The EMCCD image sensors can thus be fabricated with a stable charge carrier multiplication gain during their operational lifetime.

EMCCD image sensor with stable charge multiplication gain

Various embodiments of the present technology may comprise a method and apparatus for an image sensor. The image sensor may be configured as a stacked image sensor with two or more chips stacked vertically. The image sensor may comprise a plurality of pixel circuits, wherein portions of the pixel circuit are arranged on separate chips. Each pixel circuit may comprise an amplifier with a first feedback network to increase the sensor sensitivity, to reduce noise in the pixel signal, and to reduce the voltage swing on the FD node. Each pixel circuit may further comprise a second feedback network to stabilize the common-mode voltage of the pixel signal amplifier.

Methods and apparatus for a CMOS image sensor with an in-pixel amplifier

Growing community of inventors

Allen, TX, United States of America

Jaroslav Hynecek