Vanguard International Semiconductor Corporation

JanMye Sung

Chih-Yuan Lu

A DRAM cell structure, and a fabrication process to create the DRAM cell structure, has been developed. The area consumed by the DRAM cell structure is reduced by vertically aligning a polysilicon word line structure, to an underlying bit line structure, and to an overlying capacitor structure. The process features creating a narrow hole in a polysilicon word line structure, and in overlying and underlying insulator layers. The narrow hole, when filled with single crystalline silicon, connects the polysilicon word line structure to an underlying bit line structure, as well as connecting to an overlying capacitor structure.

Method fabricating a DRAM cell with an area equal to four times the used minimum feature

A process for fabricating a DRAM cell, with an area equal to five times the minimum feature, squared, (5F,), has been developed. The process features the use of selectively formed, N&plus; single crystalline, silicon plugs, on underlying source/drain regions. The N&plus; single crystalline, silicon plugs, epitaxial deposited, are used to connect overlying crown shaped capacitor structures, to underlying source/drain region, as well as to connect a bit line metal structure, to another source/drain region.

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Yang-May, Taiwan

JanMye Sung