Vanguard International Semiconductor Corporation

Etron Technology, Inc.

Janmye Sung

Chih-Yuan Lu

Ing-Ruey Liaw

Erik S Jeng

Howard C Kirsch

Nicky C Lu

Chun-Yao Chen

Ming-Hong Kuo

Howard Clayton Kirsch

A process for fabricating a capacitor over bitline, DRAM device, using a self-aligned contact opening, through, and between the bitline structures, and featuring the formation of insulator spacers, on the sidewall of the bitline structures, formed after the opening of the self-aligned contact, has been developed. The self-aligned contact opening, located through the bitline structures, allows an increase in DRAM cell density to be achieved. The formation of insulator spacers, on the sidewall of the bitline structures, formed after the opening of the self-aligned contact, in a silicon oxide layer, allows silicon oxide to be used as the spacer material, thus resulting in capacitance decrease when compared to counterparts fabricated using silicon nitride spacers.

Method of fabricating a self aligned contact for a capacitor over

A method of creating a capacitor over bit line structure, used for high density, DRAM designs, has been developed. The process consists of creating a straight bit line shape, connected to an underlying polysilicon contact plug structure, which in turn contacts an underlying source and drain region. A storage node contact hole is opened through insulator layers and through the straight bit line shape. After passivation of the storage node contact hole with silicon nitride spacers, a storage node structure is formed on an overlying insulator layer, as well as in the storage node contact hole, overlying and contacting another polysilicon contact plug.

Capacitor over bit line structure using a straight bit line shape

A method for making capacitor-over-bit line (COB) DRAM using a self-aligned contact etching technology is achieved. After forming FET gate electrodes, sidewall spacers are formed from a first Si.sub.3 N.sub.4 etch-stop layer, while a portion of the Si.sub.3 N.sub.4 is retained as an etch-stop layer on the source/drain areas. Self-aligned contact openings are etched in a first oxide layer to the source/drain areas, and polysilicon landing plugs are formed in all the self-aligned openings. A second oxide layer is deposited and contact holes are etched to the landing plugs for bit lines. A polycide layer having a cap layer is deposited and patterned to form bit lines. A third Si.sub.3 N.sub.4 etch-stop layer is conformally deposited over the bit lines and patterned to form openings over the landing plugs for the capacitor node contacts while forming Si.sub.3 N.sub.4 sidewall spacers on the bit lines exposed in the openings. A third oxide layer is deposited, and openings having relaxed alignment tolerances, can be etched to the capacitor node contacts because the underlying third etch-stop layer prevents overetching. A conducting layer is deposited and etched back to form bottom electrodes in the openings, and the third oxide layer is removed, while the Si.sub.3 N.sub.4 etch-stop layers prevents over-etching. An interelectrode dielectric layer is deposited, and capacitor top electrodes are formed.

Method for fabricating capacitor-over-bit-line dynamic random access

A process for fabricating a DRAM cell has been developed, in which two interlaced patterns, each comprised of capacitor node contact holes and bit line contact holes, are independently created, each using a specific photolithographic mask, and a specific photolithographic procedure. The two interlaced patterns allow the creation of the capacitor node contact images, and the bit line contact holes images, to be formed in a thin polysilicon layer, with minimum spacing between contact images. Capacitor node contact holes, as well as bit line contact holes, are than formed in an insulator layer, via a dry etching procedure, using the patterned thin polysilicon layer as a mask. The use of specific masks, or of the interlaced pattern, allows the minimum spacing, between a capacitor node contact hole, and a bit line contact hole, to be limited only by the overlay between photolithographic masks.

Design and a novel process for formation of DRAM bit line and capacitor

A process for fabricating a DRAM chip, featuring low resistance bit line structures, in a peripheral region, and a cell array containing bit line structures exhibiting low bit line to bit line coupling capacitance, has been developed. The process features creating a first damascene opening, in insulator layers in the peripheral region of the DRAM cell, in which the top portion of the first damascene opening is comprised of a deep trench shape, allowing for low resistance bit line structures, when filled with a conductive material. The process also features the creation of second damascene openings, in an insulator layer in the cell array region of the DRAM chip, with the top portion of the second damascene openings exhibiting a shallow trench shape, again allowing bit line structures to be created after filling again with a conductive layer, but with low bit line to bit line coupling capacitance, achieved as a result of the thin metal fill, in the shallow trench opening.

Method for fabricating low resistance bit line structures, along with

An improved DRAM cell using a novel buried reservoir capacitor is achieved. The method forms an array of N.sup.+ doped regions in a substrate. P-wells are formed in an epitaxy layer on the substrate. A field oxide (FOX) is formed surrounding the device areas aligned over the N.sup.+ regions. Holes are etched in the epi layer to the N.sup.+ regions, and a selective wet etch removes the N.sup.+ doped regions to form cavities. A thin dielectric layer is deposited on the cavity walls, and an N.sup.+ polysilicon layer is deposited and polished back to form the buried reservoir capacitors. The N.sup.+ polysilicon in the holes forms the capacitor node contacts for the FETs in the device areas. The array of DRAM cells is completed by growing a gate oxide, depositing and patterning a first polycide layer to form FET gate electrodes on the device areas over the capacitors, thereby providing increased capacitance while reducing the cell area. Lightly doped source/drain (LDD) areas, sidewall spacers and heavily doped source/drain contacts are formed for the FETs. A node strap is formed between one source/drain contact and the node contact to make good electrical contact. An insulating layer is deposited having bit line contact holes, and a second polycide layer is patterned to form the bit lines for the DRAM.

Method of fabricating a buried reservoir capacitor structure for

A process for fabricating a high density, capacitor over bit line, DRAM cell, using 8F.sup.2 technology, has been developed. The process features self-alignment of a tungsten bit line structure, to polycide word lines, and self-alignment of a capacitor node structure, to both tungsten bit lines, and to polycide word line structures. Self-alignment is accomplished by opening contact holes between polycide gate structures, and between tungsten bit line structures, which are coated with silicon nitride spacers, followed by filling with polysilicon plugs, which in turn contact underlying regions of the semiconductor substrate.

Method for fabrication of a one gigabit capacitor over bit line DRAM

A process for creating a region of high performance logic devices, and a region of low cost memory devices, on a single semiconductor chip, has been developed. The process features CMOS logic devices, comprised of polycide gate structures, residing on a thin silicon dioxide gate insulator layer. An N type polysilicon layer, used as part of a polycide structure, is used with the N channel CMOS devices, while a P type polysilicon layer, is used with the P channel CMOS devices. DRAM memory devices are comprised of polycide gate structures, featuring only an N type polysilicon layer, on a silicon dioxide gate insulator layer, that is thicker than the gate silicon oxide layer used with the high performance logic devices. A minimum of additional photolithographic masking procedures is used to improve the performance of the logic region, one mask to allow specific polycide gate structures to be created with either P type or N type polysilicon, and another additional mask used to allow different gate insulator layers to be formed in each specific region. A large angle, ion implantation procedure, is used to form lightly doped source and drain regions, under the silicon nitride spacers on the sides of polycide gate structures, in both logic and DRAM memory regions.

Process for fabricating a high performance logic and embedded dram

The present invention provides a method for fabricating a multiple pillar shaped capacitor which has pillars of a smaller dimension than the resolution of the photolithography tool. The invention has two embodiments for forming the pillars and third embodiment for patterning a conductive layer into discrete bottom electrodes. The method begins by forming a conductive layer on a first planarization layer. For the first embodiment, the pillars are formed using a photolithography mask with a pattern of spaced transparent areas. The dimensions of the spaced transparent areas and distances between the spaced transparent areas are smaller then that of the resolution of the lithographic tool. Spaced oxide islands are formed with the mask and are used as an etch mask to form spaced pillars from the conductive layer. The second embodiment for forming the pillars involves using small titanium silicide islands as an etch mask to define the pillars. The third embodiment uses two resist layers and a photo mask shifting (offset) technique to form small spaces between the electrodes. Lastly, a capacitor dielectric layer and a top electrode are formed over the bottom electrodes thereby completing the capacitor with a pillar structure.

Method for forming a capacitor with a multiple pillar structure

A DRAM device structure, using a stacked capacitor configuration, has been developed. The stacked capacitor structure is comprised of a lower, polysilicon storage node, a thin composite dielectric layer, and an overlying capacitor plate, comprised of a composite layer of an overlying polysilicon layer, on a thin amorphous silicon layer, contacting an N type source and drain region, in a semiconductor substrate. A bit line contact structure, comprised of a metal silicide - polysilicon composite structure, is also used in the DRAM device structure. A PFET device, adjacent to the stacked capacitor DRAM device, featuring a two part contact structure, to P type source and drain regions, comprised of a wide top, aluminum - copper shape, overlying a narrower tungsten stud, is also used in this invention.

Reduced mask DRAM process

The invention is a method of forming a reduced cost DRAM. The process has two embodiments for forming twin wells and two embodiments for forming pillar shaped capacitor electrodes. The twin well embodiments are simple low cost processes. The embodiments for forming the electrode pillars begin by forming a tungsten silicide conductive layer on a first planarization layer. For the first embodiment, the pillars are formed using a photolithography mask with a pattern of spaced transparent areas. The dimensions of the spaced transparent areas and distances between the spaced transparent areas are smaller that the resolution of the lithographic tool. Spaced oxide islands are formed with the mask and are used as an etch mask to form spaced pillars from the conductive layer. This first embodiment for fabricating the multiple pillar capacitor forms pillars of a smaller dimension than the resolution of the photolithography tool. The second embodiment for forming the pillars involves using small titanium silicide islands as an etch mask to define the pillars.

Method of forming a low cost DRAM cell with self aligned twin tub CMOS

A process for fabricating stacked capacitor, DRAM devices, wherein the surface area of the capacitor is significantly increased as a result of sidewall processes, has been developed. The process is highlighted by deposition of polysilicon, to be used for the lower electrode of the stacked capacitor structure, on specific underlying insulator shapes. As a result of the severe underlying insulator topography, a significant portion of the polysilicon forms on the sides of the underlying insulator shapes, creating a significant increase in the lower electrode surface area, which relates to marked increases in capacitance and device signal.

Dram cell capacitor fabrication method

A method for forming memory cells, featuring a bit line, embedded in an insulator filled, shallow trench, has been developed. Self-alignment of the buried bit line, to a source and drain region of a transfer gate transistor, is obtained via outdiffusion of a doped polysilicon layer, used as part of the buried bit line, composite layer.

Memory cell array with a self-aligned, buried bit line

A process for fabricating CMOS devices has been developed, in which decreased cycle time has been achieved, via a reduction in photomasking steps. The low cycle time CMOS process features the use of only one photo mask to create both the lightly doped, as well as the heavily doped N type, source and drain regions, by performing both implantations, after creation of the insulator sidewall spacer. In addition the P type source and drain regions are formed, using an oxide layer as a blockout for the P well region, thus eliminating the use of another photomasking procedure.

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Yang Mei, Taiwan

Janmye Sung