Taiwan Semiconductor Manufacturing Comp. Ltd.

Jang Jung Lee

Shih-Wei Hung

Dong Gui

Wen-Chung Liu

Wei-Shan Hu

Duen-Huei Hou

Che-Liang Li

Yung-Huei Lee

Chia-Fang Wu

Chou-Jie Tsai

Wei-Cheng Chu

The disclosure is directed to techniques in preparing an atom probe tomography ('APT') specimen. The disclosed techniques form an APT specimen or sample directly on a DUT region on a wafer. The APT specimen is formed integrally to the substrate or the support structure, e.g., a carrier, under the APT specimen. A laser patterning is conducted to form a trench in the DUT and one or more bump structures in the trench. The laser patterning is relatively coarse and forms a coarse surface texture on each of the bump structures. A low-kV gas ion milling using a dual-beam focused ion beam (“FIB”) microscopes is then conducted to shape the bump structures into APT specimen.

Atom probe tomography specimen preparation

A semiconductor metrology tool for analyzing a sample is disclosed. The semiconductor metrology tool includes a particle generation system, a local electrode, a particle capture device, a position detector, and a processor. The particle generation system is configured to remove a particle from a sample. The local electrode is configured to produce an attractive electric field and to direct the removed particle towards an aperture of the local electrode. The particle capture device is configured to produce a repulsive electric field around a region between the sample and the local electrode and to repel the removed particle towards the aperture. The position detector is configured to determine two-dimensional position coordinates of the removed particle and a flight time of the removed particle. The processor is configured to identify the removed particle based on the flight time.

Detection systems in semiconductor metrology tools

The disclosure is directed to techniques in preparing an atom probe tomography ('APT') specimen. The disclosed techniques form an APT specimen or sample directly on a DUT region on a wafer. The APT specimen is formed integrally to the substrate or the support structure, e.g., a carrier, under the APT specimen. A laser patterning is conducted to form a trench in the DUT and one or more bump structures in the trench. The laser patterning is relatively coarse and forms a coarse surface texture on each of the bump structures. A low-kV gas ion milling using a dual-beam focused ion beam ('FIB') microscopes is then conducted to shape the bump structures into APT specimen.

Embodiments disclosed herein relate generally to methods for measuring a characteristic of a substrate. In an embodiment, the method includes scanning over the substrate with a scanning probe microscope, the substrate having fins thereon, the scanning obtaining images showing respective fin top regions of the fins, the scanning probe microscope interacting with respective portions of sidewalls of the fins by a scanning probe oscillated during the scanning, selecting images obtained at a predetermined depth below the fin top regions to obtain a line edge profile of the fins, by a processor-based system, analyzing the line edge profile of the fins using power spectral density (PSD) method to obtain spatial frequency data of the line edge profile of the fins, and by the processor-based system, calculating line edge roughness of the fins based on the spatial frequency data.

Line edge roughness analysis using atomic force microscopy

Systems and methods are provided for determining defects in a semiconductor structure sample that is prepared for analysis by microscopy. A semiconductor structure sample preparation and analysis system includes a semiconductor structure sample that includes a structure, a protective capping layer on the structure, and a gap filler material on the protective capping layer. A microscopy apparatus acquires an image of the semiconductor structure sample. Sample defect recognition circuitry determines the presence of a defect in the semiconductor structure sample based on the acquired image.

Systems and methods for semiconductor structure sample preparation and analysis

The disclosure is directed to techniques in preparing an atom probe tomography ('APT') specimen. A structure in a semiconductor device is identified as including a test object for an APT procedure. A target region is identified in the structure where an APT specimen will be obtained. The target region is analyzed to determine whether a challenging component feature exists therein. A challenging component may include a hard-to-evaporate material, a hollow region, or a material unidentifiable with respect to the test object, or other structural features that pose a challenge to a successful APT analysis. If it is determined that a challenging component exists in the target region, the challenging component is replaced with a more suitable material before the APT specimen is prepared.

Provided is a method of fabricating a semiconductor device. The method includes providing a substrate. The method includes forming a portion of an interconnect structure over the substrate. The portion of the interconnect structure has an opening. The method includes obtaining a boron-containing gas that is free of a boron-10 isotope. The method includes filling the opening with a conductive material to form a contact. The filling of the opening is carried out using the boron-containing gas. Also provided is a semiconductor device. The semiconductor device includes a substrate. The semiconductor device includes an interconnect structure formed over the substrate. The semiconductor device includes a conductive contact formed in the interconnect structure. The conductive contact has a material composition that includes Tungsten and Boron, wherein the Boron is aB-enriched Boron.

Growing community of inventors

Hsinchu, Taiwan

Jang Jung Lee