Samsung Electronics Co., Ltd.

Jang Gn Yun

Sun Young Kim

Sung Min Hwang

Jae Duk Lee

Joon Sung Lim

Su Jin Park

Hoo Sung Cho

Se Jun Park

Zhiliang Xia

Jae Ho Jeong

Hyo Seok Woo

Ahn Sik Moon

Hyun Sook Yoon

A memory device includes gate electrode layers stacked on an upper surface of a substrate and each including a plurality of unit electrodes extending in a first direction, and a plurality of connecting electrodes connecting the unit electrodes to each other. The memory device also includes channel structures extending through the gate electrode layers in a direction perpendicular to the upper surface of the substrate, first common source lines extending in the first direction and interposed between the unit electrodes, and second common source lines extending in the first direction between the first common source lines and each having a first line and a second line separated from each other in the first direction by the connecting electrodes.

Memory device

A three-dimensional semiconductor device includes a stacked structure on a lower structure, the stacked structure including a lower group including gate electrodes vertically stacked and spaced apart from each other, and an upper group including gate electrodes vertically stacked and spaced apart, the lower group and the upper group being vertically stacked, and a vertical structure passing through the stacked structure. The vertical structure may include a vertical core pattern, a vertical buffer portion therein, and a surrounding vertical semiconductor layer, the vertical structure may include a lower vertical portion passing through the lower group and an upper vertical portion passing through the upper group, an upper region of the lower vertical portion may have a width greater than that of a lower region of the upper vertical portion. The vertical buffer portion may be in the lower vertical portion and below the upper vertical portion.

Three-dimensional semiconductor device

A memory device includes a pair of common source lines disposed on a substrate spaced apart from each other and extended in a first direction; a plurality of ground select lines disposed between the pair of common source lines, extended in the first direction, and disposed on the same level; a plurality of word lines disposed on the plurality of ground select lines between the pair of common source lines, extended in the first direction, and disposed on the same level, at least a portion of the plurality of word lines being connected by a connection electrode; and a plurality of first separation insulating patterns disposed between individual ground select lines of a portion of the plurality of ground select lines and extended in the first direction. The at least portion of the plurality of word lines is connected by a connection electrode.

Memory devices

A semiconductor device is provided including a resistor structure on a semiconductor substrate. The resistor structure includes pad portions and a resistor body connecting the pad portions. The pad portions each have a width greater than a width of the resistor body. The pad portions each include a pad pattern and a liner pattern covering a sidewall and a lower surface of the pad pattern. The resistor body extends laterally from the liner pattern. The pad pattern includes a different material from the resistor body and the liner pattern.

Semiconductor devices including resistors

A semiconductor device and a method of forming the same are provided. The semiconductor device includes interlayer support patterns sequentially stacked on a substrate, horizontal conductive patterns sequentially stacked on the substrate, and an interlayer insulating layer disposed between the interlayer support patterns, extending between the horizontal conductive patterns, and disposed in parallel with a surface of the substrate. The interlayer insulating layer is in contact with the interlayer support patterns. A conductive structure extends in a direction perpendicular to the substrate. Vertical structures extending through the horizontal conductive patterns and the interlayer insulating layer are formed.

Semiconductor device including interlayer support patterns on a substrate

A semiconductor device includes a gate stack including gate electrodes stacked vertically on a substrate. Channel holes penetrate through the gate stack to extend vertically to the substrate. Each of the channel holes includes a channel region. First channel pads are each disposed at an end of a respective channel hole opposite the substrate. Each of the first channel pads includes at least one first conductivity-type impurity. Second channel pads are each disposed at an end of a respective channel hole opposite the substrate. Each of the second channel pads includes at least one second conductivity-type impurity.

Semiconductor device having channel holes

A memory device includes a cell region including a channel region extending to be perpendicular to an upper surface of a substrate, a plurality of gate electrode layers stacked on the substrate adjacently to the channel region, a peripheral circuit region including a first active region disposed in the vicinity of the cell region, a second active region having an area larger than an area of the first active region, a plurality of first contacts connected to the first active region, and a plurality of second contacts connected to the second active region. A distance between the plurality of first contacts is less than that between the plurality of second contacts.

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Hwaseong-si, South Korea

Jang Gn Yun