Samsung Electronics Co., Ltd.

Amsung Electronics Co., Ltd.

Jang-Gn Yun

Joon-Sung Lim

Jaesun Yun

Sung-Min Hwang

Jae-Duk Lee

Zhiliang Xia

Se-Jun Park

Ahn-Sik Moon

Sunghoi Hur

Hoosung Cho

Sunil Shim

Kwang Soo Seol

Jungdal Choi

Kwang-Soo Seol

Jaehoon Jang

Sunyoung Kim

Jung-dal Choi

Hoo-Sung Cho

Jai-Hyuk Song

Jeonghyuk Choi

Young-woo Kim

Youngwoo Park

Hong-soo Kim

Hongsoo Kim

Jin-Kyu Kang

Joon Sung Lim

Jae-Sun Yun

Kyu-Baik Chang

Jaeho Jeong

Kyoil Koo

Cheol Ryou

Jae-ho Ahn

Euido Kim

Aaron Park

Su-Ok Yun

Sunghoon Bae

An integrated circuit device includes channel structures extending from a substrate in a vertical direction, memory cell strings disposed along the plurality of channel structures, gate lines spaced apart from one another in the vertical direction and including erase control lines and string selection lines, and driving transistors including erase control driving transistors connected to the erase control lines and string selection driving transistors connected to the string selection lines.

Integrated circuit device

A vertical memory device includes a channel, a dummy channel, a plurality of gate electrodes, and a support pattern. The channel extends in a first direction perpendicular to an upper surface of a substrate. The dummy channel extends from the upper surface of the substrate in the first direction. The plurality of gate electrodes are formed at a plurality of levels, respectively, spaced apart from each other in the first direction on the substrate. Each of the gate electrodes surrounds outer sidewalls of the channel and the dummy channel. The support pattern is between the upper surface of the substrate and a first gate electrode among the gate electrodes. The first gate electrode is at a lowermost one of the levels. The channel and the dummy channel contact each other between the upper surface of the substrate and the first gate electrode.

Vertical memory devices and methods of manufacturing the same

A semiconductor device may include a cell gate conductive pattern in a cell array area that extends to a step area, a cell vertical structure in the cell array area that extends through the cell gate conductive pattern, a cell gate contact structure on the cell gate conductive pattern in the step area, a cell gate contact region in the cell gate conductive pattern and aligned with the cell gate contact structure, a first peripheral contact structure spaced apart from the cell gate conductive pattern, a second peripheral contact structure spaced apart from the first peripheral contact structure, a first peripheral contact region under the first peripheral contact structure, and a second peripheral contact region under the second peripheral contact structure. The cell gate contact region may include a first element and a remainder of the cell gate conductive pattern may not substantially include the first element.

Semiconductor devices and methods for forming the same

A semiconductor device includes a cell semiconductor pattern disposed on a semiconductor substrate. A semiconductor dummy pattern is disposed on the semiconductor substrate. The semiconductor dummy pattern is co-planar with the cell semiconductor pattern. A first circuit is disposed between the semiconductor substrate and the cell semiconductor pattern. A first interconnection structure is disposed between the semiconductor substrate and the cell semiconductor pattern. A first dummy structure is disposed between the semiconductor substrate and the cell semiconductor pattern. Part of the first dummy structure is co-planar with part of the first interconnection structure. A second dummy structure not overlapping the cell semiconductor pattern is disposed on the semiconductor substrate. Part of the second dummy structure is co-planar with part of the first interconnection structure. A conductive shielding pattern is disposed between the cell semiconductor pattern and the semiconductor substrate and above the first circuit and the first interconnection structure.

Semiconductor device including dummy patterns and peripheral interconnection patterns at the same level

Integrated circuit devices may include a plurality of word line structures and a plurality of insulating films that are stacked alternately. Sides of the plurality of word line structures and the plurality of insulating films define a side of a channel hole extending through the plurality of word line structures and the plurality of insulating films. The devices may also include a blocking dielectric film on the side of the channel hole, and a plurality of charge storage films on the blocking dielectric film and on the sides of the plurality of word line structures, respectively. Each of the plurality of charge storage films may include a first charge storage film and a second charge storage film sequentially stacked on a respective one of the sides of the plurality of word line structures. A surface of the second charge storage film may include a recess in a middle portion thereof.

Integrated circuit devices and methods of manufacturing the same

A vertical memory device includes conductive lines on a substrate, first and second semiconductor patterns, first and second pads, first and second electrodes, a third electrode, and a first division pattern. The conductive lines are stacked in a vertical direction and extend in a first direction. The first and second semiconductor patterns extend through the conductive lines in the vertical direction. The first and second pads are formed on the first and second semiconductor patterns. The first and second electrodes are electrically connected to the first and second pads. The third electrode is electrically connected to a first conductive line of the conductive lines. The first division pattern extends in a second direction, and extends through and divides the first conductive line. In a plan view, the first and second semiconductor patterns and the first conductive line are disposed at one side of the first division pattern.

Provided are a semiconductor device, a method of manufacturing the semiconductor device, and an electronic system adopting the same. The semiconductor device includes a semiconductor pattern, which is disposed on a semiconductor substrate and has an opening. The semiconductor pattern includes a first impurity region having a first conductivity type and a second impurity region having a second conductivity type different from the first conductivity type. A peripheral transistor is disposed between the semiconductor substrate and the semiconductor pattern. A first peripheral interconnection structure is disposed between the semiconductor substrate and the semiconductor pattern. The first peripheral interconnection structure is electrically connected to the peripheral transistor. Cell gate conductive patterns are disposed on the semiconductor pattern. Cell vertical structures are disposed to pass through the cell gate conductive patterns and to be connected to the semiconductor pattern. Cell bit line contact plugs are disposed on the cell vertical structures. A bit line is disposed on the cell bit line contact plugs. A peripheral bit line contact structure is disposed between the bit line and the first peripheral interconnection structure. The peripheral bit line contact structure crosses the opening of the semiconductor pattern.

Semiconductor devices

Semiconductor memory devices are provided. A semiconductor memory device includes a memory cell region and an insulator on a portion of the memory cell region. The semiconductor memory device includes a stress relief material that is in the insulator and is between the memory cell region and another region of the semiconductor memory device.

Semiconductor memory devices including a stress relief region

An integrated circuit device includes word line structures, insulating structures, a channel hole, and charge trap patterns. The word line structures and the insulating structures are interleaved with each other and extend in a horizontal direction parallel to a main surface of a substrate, and overlap one another in a vertical direction. The channel hole passes through the word line structures and the insulating structures in the vertical direction. The charge trap patterns are located in the channel hole, and are spaced apart from one another in the vertical direction with a local insulating region therebetween.

Integrated circuit device and method of manufacturing the same

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Hwaseong-si, South Korea

Jang-Gn Yun