Samsung Electronics Co., Ltd.

Jang-Eun Heo

Chang-ki Hong

Dong-Hyun Im

Suk-Hun Choi

Yoon-Ho Son

Ik-Soo Kim

Byoung-Jae Bae

Choong-Man Lee

Dong-chul Yoo

Hong-Sik Yoon

Young-Moon Choi

Sun-Woo Lee

Kyung-rae Byun

Ji-Eun Lim

Sung-Ju Lee

A phase-change memory device including a first contact region and a second contact region formed on a semiconductor substrate. A first insulating layer with a first contact hole and a second contact hole is disposed on the semiconductor substrate, exposing the first and second contact regions. A first conductive layer is disposed on the first insulating interlayer to fill the first and the second contact holes. A first protection layer pattern and a lower wiring protection pattern are disposed on the first conductive layer. A first contact with a first electrode and a second contact with a lower wiring are disposed so as to connect the first and second contact regions. A second protection layer with a second electrode is disposed on the first protection layer pattern and the lower wiring protection pattern. A via filled with a phase-change material is disposed between the first electrode and the second electrode.

Phase-change memory device using a variable resistance structure

A device includes an insulating layer on a substrate having a lower conductive pattern, the insulating layer having a contact hole that penetrates the insulating layer and exposes a portion of the lower conductive pattern, a catalytic pattern having a first portion on the exposed portion of the lower conductive pattern and a second portion on a sidewall of the contact hole, a spacer on the sidewall of the contact hole, wherein the second portion of the catalytic pattern is disposed between the spacer and the sidewall, and a contact plug in the contact hole and contacting the catalytic pattern, the contact plug being a carbon nanotube material.

Device including contact structure and method of forming the same

A method of forming a ferroelectric layer is provided. A metal-organic source gas is provided into a chamber into which an oxidation gas is provided for a first time period to form ferroelectric grains on a substrate. A ferroelectric layer is formed by performing at least twice a step of providing a metal-organic source gas into the chamber during the first time period using a pulse method to grow the ferroelectric grains.

Methods of forming a ferroelectric layer and methods of manufacturing a ferroelectric capacitor including the same

In methods of manufacturing a variable resistance structure and a phase-change memory device, after forming a first insulation layer on a substrate having a contact region, a contact hole exposing the contact region is formed through the first insulation layer. After forming a first conductive layer on the first insulation layer to fill up the contact hole, a first protection layer pattern is formed on the first conductive layer. The first conductive layer is partially etched to form a contact and to form a pad on the contact. A second protection layer is formed on the first protection layer pattern, and then an opening exposing the pad is formed through the second protection layer and the first protection layer pattern. After formation of a first electrode, a phase-change material layer pattern and a second electrode are formed on the first electrode and the second protection layer.

Method of manufacturing a variable resistance structure and method of manufacturing a phase-change memory device using the same

A method of fabricating a ferroelectric device includes forming a ferroelectric layer on a substrate in a reaction chamber. An inactive gas is provided into the reaction chamber while unloading the substrate therefrom to thereby substantially inhibit formation of an impurity layer on the ferroelectric layer.

Methods of fabricating ferroelectric devices

A probe array may be fabricated by forming probes arranged on a sacrificial substrate, forming a probe substrate above the probes, and removing the sacrificial substrate. In one embodiment, first probes may be two-dimensionally formed in row and column directions on a sacrificial substrate. Second probes may be formed between the first probes arranged in the row direction such that a distance between the first and second probes is smaller than the resolution limit in a lithography process. A probe substrate may be formed on the sacrificial substrate having the first and second probes, and the sacrificial substrate may be removed.

High-density probe array

An integrated circuit device includes a storage cell including an upper electrode and a lower electrode on a substrate, and a conductive hard mask pattern directly on the upper electrode of the storage cell opposite the lower electrode. The upper electrode is formed of a metal softer than the conductive hard mask pattern. The device further includes an interlayer on the substrate having an alignment key recess therein. The alignment key recess extends towards the substrate beyond a depth of the upper electrode. An alignment key pattern may extend towards the substrate beyond the depth of the upper electrode on opposing sidewalls and on a surface therebetween of the alignment key recess. The alignment key pattern may have a distinct step difference between portions thereof on the opposing sidewalls and portions thereof on the surface therebetween. Related methods are also discussed.

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Seoul, South Korea

Jang-Eun Heo