Taiwan Semiconductor Manufacturing Comp. Ltd.

Other

Jane-Bai Lai

Chung-Shi Liu

Chen-Hua Douglas Yu

Syun-Ming Jang Jang

Mong-Song Liang

Lih-Juann Chen

Tien-I Bao

Ying-Lang Wang

Chung-Long Chang

Szu-An Wu

Yi-Lung Cheng

Wen-Kung Cheng

Chun-Ching Tsan

Hui-Ling Wang

Pei-Fen Chou

Lih-Juan Chen

A plasma treatment method which is capable of extending the MTF (mean-time-to-failure) of metal interconnects fabricated on a semiconductor wafer substrate, is disclosed. The invention includes providing a trench typically in a dielectric layer on a substrate; depositing a metal in the trench; and exposing the metal to a nitrogen-based plasma. The plasma-treatment step accelerates grain growth and re-orients the grains in the metal to a closely-packed crystal orientation texture which approaches or approximates the &#x3c;111&#x3e; crystal orientation texture of copper.

Plasma treatment method for electromigration reduction

A method of etching a low dielectric constant material with an aqueous solution of hydrofluoric acid and hydrochloric acid. The etching solution is particularly useful on low dielectric constant materials that are water repulsive or hydrophobic. The weight ratio of hydrofluoric acid to hydrochloric acid in the aqueous solution ranges from 1:3 to 4:1.

Method of wet etching low dielectric constant materials

Cu, for its rather low resistivity, will be widely used in sub-quarter micron meter ULSI devices. However, it is well known that Cu is easy to be corroded as exposed in air. In packaging of chips the bonding pads making of Cu will thus oxides. In addition, the reaction between Au-ball and Cu pads is very poor. On the other hand, a native AlOx layer, about 3-4 nm in thickness, will form as Al exposes in air; the formed layer is inert and is capable of protecting Al from corrosion. Furthermore, the reaction between Au-ball and Al was very well. Therefore, with the methods of the present invention, Al or AlCu as a glue and protection layer is implemented on Cu bonding pads for successful Au wiring.

Method of improving the bondability between Au wires and Cu bonding pads

A method and a solution for preparing SEM samples comprising low-K dielectric materials. The process begins by providing a SEM sample comprising low-K dielectric material and silicon oxide material. A solution is formed for preparing (staining and etching) the SEM sample by adding NH F (s) to a solution comprising CH COOH having a concentration of about 98% at a ratio of about 1 g NH F (s):20 ml CH COOH, then stirring until the NH F (s) is thoroughly dissolved. Alternatively, the NH F (s) can be added to a solution comprising HNO having a concentration of about 70% and CH COOH having a concentration of about 98%, with a volume ratio of about 15 ml HNO :20 ml CH COOH. The NH F (s) is added at a ratio of about 1 g NH F (s):35 ml CH COOH and HNO , and stirred until the NH F (s) is thoroughly dissolved. The SEM sample is then etched in this solution for about 3 seconds, whereby the low-K dielectric material and silicon oxide material have similar etch rates with good selectivity to metals.

Method and solution for preparing SEM samples for low-K materials

Cu, for its rather loe resistivity, will be widely used in sub-quarter micron meter ULSI devices. However, it is well known that Cu is easy to be corroded as exposed in air. In packaging of chips the bonding pads making of Cu will thus oxides. In addition, the reaction between Au-ball and Cu pads is very poor. On the other hand, a native AlOx layer, about 3-4 nm in thickness, will form as Al exposes in air; the formed layer is inert and is capable of protecting Al from corrosion. Furthermore, the reaction between Au-ball and Al was very well. Therefore, with the methods of the present invention, Al or AlCu as a glue and protection layer is implemented on Cu bonding pads for successful Au wiring.

An improved SALICIDE process is described wherein the transformation temperature to a lower resistivity suicide structure is reduced by first coating with a layer of a silicon-germanium alloy prior to the deposition of the titanium layer. Provided there is at least 40 atomic percent of germanium in the alloy a second RTA at a temperature no higher than about 650&deg; C. may be effectively used. The resulting ternary alloy has a resistivity of about 15-20 microhm cm which corresponds to a sheet resistance of about 3-3.5 ohms per square. The ability to achieve low sheet resistance after annealing at such a low temperature becomes increasingly more important as device dimensions decrease since the second RTA becomes increasingly more likely to result in agglomeration of the silicidelayer.

Method of reducing phase transition temperature by using silicon-germanium alloys

A method of forming an interconnect, comprising the following steps. A semiconductor structure is provided that has an exposed first metal contact and a dielectric layer formed thereover. An FSG layer having a predetermined thickness is then formed over the dielectric layer. A trench, having a predetermined width, is formed within the FSG layer and the dielectric layer exposing the first metal contact. A barrier layer, having a predetermined thickness, may be formed over the FSG layer and lining the trench side walls and bottom. A metal, preferably copper, is then deposited on the barrier layer to form a copper layer, having a predetermined thickness, over said barrier layer covered FSG layer, filling the lined trench and blanket filling the barrier layer covered FSG layer. The copper layer, and the barrier layer on said upper surface of said FSG layer, are planarized, exposing the upper surface of the FSG layer and forming a planarized copper filled trench. The FSG layer and planarized copper filled trench are then processed by either: (1) annealing from about 400 to 450.degree. C. for about one hour, then either NH.sub.3 or H.sub.2 plasma treating; or (2) Ar.sup.+ sputtering to ion implant Ar.sup.+ to a depth of less than about 300 .ANG. in the fluorinated silica glass layer, whereby any formed Si--OH bonds and copper oxide (metal oxide) are removed. A dielectric cap layer, having a predetermined thickness, is then formed over the processed FSG layer and the planarized copper filled trench.

Methods to improve copper-fluorinated silica glass interconnects

A method for fabricating a copper interconnect structure, using a low resistivity Cu.sub.3 Ge intermetallic layer, as an adhesive layer, has been developed. Following an in situ, CVD of a titanium nitride barrier layer, a germanium layer, and a copper layer, an anneal procedure is used to form the Cu.sub.3 Ge intermetallic layer, with the intermetallic layer, located between the underlying titanium nitride barrier layer, and the overlying copper layer. The Cu.sub.3 Ge intermetallic layer can also be formed in situ, during deposition, if the deposition temperature exceeds 150.degree. C. Cu.sub.3 Ge layer exhibits a resistivity of about 5E-6 ohm - cm. A second iteration of this invention allows a thick copper layer to be plated on a thin copper seed layer, only on the top surface of a semiconductor substrate. This iteration, also incorporating the low resistivity, Cu.sub.3 Ge intermetallic, and the adhesive layer, prevents copper from being plated on the beveled edge of the semiconductor substrate.

Use of a low resistivity Cu.sub.3 Ge interlayer as an adhesion promoter

A method for fabricating a copper interconnect structure, using a Cu.sub.3 Ge intermetallic layer, as an adhesive layer, has been developed. Following the deposition of a copper seed layer, an ion implantation procedure is performed, placing germanium ions in a copper seed layer. After deposition of a thick copper layer, an anneal cycle, performed before or after deposition of the thick copper layer, is used to create a Cu.sub.3 Ge intermetallic layer at the interface between a copper seed layer and a titanium nitride barrier layer. A second embodiment of this invention uses a tilted, germanium ion implantation procedure, used to avoid the placement of germanium ions in a copper seed layer, at the bottom of a contact hole, thus avoiding possible implantation damage, to active device regions, exposed in the bottom of the contact hole.

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Hsin-Chu, Taiwan

Jane-Bai Lai