Fujian Jinhua Integrated Circuit Co., Ltd.

Janbo Zhang

Yu-Cheng Tung

Li-Wei Feng

Enping Cheng

Tsung-Wen Chen

Chia-Yi Chu

Shih-Han Hung

Chao-Wei Lin

Ken-Li Chen

The present disclosure provides a semiconductor device and a fabricating method thereof, the semiconductor device includes a substrate, a capacitor structure, a sidewall high-k dielectric layer and a supporting structure. The capacitor structure is disposed on the substrate, and includes a plurality of columnar bottom electrodes, a capacitor dielectric layer and a top electrode layer, wherein each of the columnar bottom electrodes includes a recess on the top. The sidewall high-k dielectric layer is disposed on two opposite sidewalls of each of the columnar bottom electrodes, wherein a portion of the capacitor dielectric layer is filled in the recess and sandwiched between the columnar bottom electrodes and the sidewalls high-k dielectric layer. The supporting structure is disposed between the adjacent ones of the columnar bottom electrodes, and includes a first supporting layer and a second supporting layer stacked from bottom to top.

Semiconductor device and fabricating method thereof

The present disclosure relates to a semiconductor memory device and a fabricating method thereof, includes a substrate, a plurality of gate structures, a plurality of isolation fins, at least one bit line, and a plug. The gate structures are disposed in the substrate, being parallel with each other along a first direction. The isolation fins are disposed on the substrate, parallel with each other and extending along the first direction, over each of the gate structures respectively. The bit line is disposed on the substrate to extend along a second direction being perpendicular to the first direction. The bit line includes a plurality of pins extending toward the substrate, being alternately arranged with the isolation fins along the second direction. The plug is disposed on the substrate, being alternately with the bit line in the first direction.

Semiconductor memory device comprises a bit line having a plurality of pins extending toward a substrate

A semiconductor device includes a substrate having a plurality of parallel active regions, an isolation structure in the substrate to separate the active regions, a buried word line disposed in the substrate and cutting through the isolation structure and the active regions, and a dielectric insert structure disposed in the substrate, directly under the buried word line and between end portions of adjacent two of the active regions. A bottom surface of the dielectric insert structure is lower than a bottom surface of the isolation structure.

Semiconductor device including dielectric insert structure directly under buried word line and method for forming the same

The present disclosure provides a semiconductor device and a method of fabricating the same, and the semiconductor device includes a substrate, active areas, and an isolation structure. The active areas are parallel and separately disposed with each other in the substrate, and each of the active areas includes an active fin and active ends disposed at two sides of the active fin. The active fin and the active ends include different materials. The isolation structure is disposed in the substrate to surround the active areas. With this arrangement, the extending area of the active areas may be improved, so as to make sure the storage node contacts formed subsequently may directly and stably contact with the active areas.

Semiconductor device and method of fabricating the same

A semiconductor structure is provided in the present invention, including a substrate with multiple recesses and active areas, multiple bit lines spaced apart in a first direction on the cell region and extending in a second direction perpendicular to the first direction, and the bit line is electrically connected to an active area in the substrate through the recess, and a dummy bit line at an outermost side of the multiple bit lines in the first direction and extending in the second direction, wherein a width of the dummy bit line in the first direction is larger than a width of the bit line in the first direction, and the bit lines and the dummy bit line have the same composition and layer structures.

Semiconductor structure and method of manufacturing the same

The present disclosure provides a semiconductor memory device and a fabricating method thereof, which includes a substrate, a plurality of buried word lines, and a plurality of storage node contacts. The substrate includes a plurality of active areas and a shallow trench isolation. The buried word lines are embedded in the substrate, across the shallow trench isolation and the active areas. The storage node contacts directly contact the active areas and include a plurality of first plugs, with each first plug including an insulating material and a conductive material stacked sequentially from bottom to top. Within the semiconductor memory device, at least one active area simultaneously contacts two of the first plugs, or a storage node pad physically contacts at least two of the first plugs. Thus, the present disclosure is beneficial on forming the semiconductor memory device with better component reliability.

Semiconductor memory device and method of fabricating the same

A semiconductor memory device including an array region and a peripheral region surrounding the array region. The array region includes a plurality of active regions and a first insulating layer disposed between the active regions. The peripheral region includes a peripheral structure, a second insulating layer surrounding the peripheral structure, and a third insulating layer surrounding the second insulating layer. At least a buried word line extends through the array region and the peripheral region, wherein a portion of the buried word line through the second insulating layer comprises a neck profile from a plan view.

Semiconductor memory device having buried word line with a neck profile portion

A dynamic random access memory device includes a substrate having a first active region, a first isolation region, a second active region, and a second isolation region arranged in order along a first direction. A first bit line is disposed on the first active region and in direct contact with the first active region. A second bit line is disposed on the second isolation region. An insulating layer is disposed between and separate the second bit line and the second isolation region. A storage node contact structure is disposed between the first bit line and the second bit line and is in direct contact with a top surface of the second active region, a sidewall of the first isolation region, and a sidewall of the second isolation region.

Dynamic random access memory device

The present disclosure relates to a semiconductor device and a method of fabricating the same, the semiconductor device including a substrate, an active structure and a shallow trench isolation. The active structure is disposed within the substrate, including a plurality of first active fragments and a plurality of second active fragments. The first active fragments and the second active fragments are parallel and separately extended along a first direction, and the second active fragments are disposed outside all of the first active fragments. The first active fragments have a same length in the first direction, being a first length, the second active fragment have a second length in the first direction, and the second length is greater than the first length.

Semiconductor device and method of fabricating the same having a second active region disposed at an outer side of a first active region

A semiconductor device includes a substrate, a plurality of active regions disposed in the substrate and respectively extending along a first direction and arranged into an array, and a plurality of isolation structures disposed in the substrate between the active regions. The isolation structures respectively comprise an upper portion and a lower portion, wherein a sidewall of the upper portion comprises a first slope, a sidewall of the lower portion comprises a second slop, and the first slope and the second slope are different. The semiconductor device further includes a plurality of semiconductor layers disposed between the upper portions of the isolation structures and the active regions.

Semiconductor device having semiconductor layers disposed between upper portions of the isolation structures and the active regions

A semiconductor memory device includes a substrate, an active structure, a shallow trench isolation and a plurality of word lines. The active structure is disposed in the substrate, and includes a plurality of first active fragments and a plurality of second active fragments extended parallel to each other along a first direction and the second active fragments are disposed outside a periphery of all of the first active fragments. The shallow trench isolation is disposed in the substrate to surround the active structure, and which includes a plurality of first portions and a plurality of second portions. The word lines are disposed in the substrate, parallel with each other to extend along a second direction, wherein at least one of the word lines are only intersected with the second active fragments, or at least one of the word lines does not pass through any one of the second portions.

Semiconductor memory device

The present disclosure relates to a method of fabricating a semiconductor device, the semiconductor device includes a substrate, a plurality of gate structures, a plurality of isolation fins, and at least one bit line. The gate structures are disposed in the substrate, with each of the gate structures being parallel with each other and extending along a first direction. The isolation fins are disposed on the substrate, with each of the isolation fins being parallel with each other and extending along the first direction, over each of the gate structures respectively. The at least one bit line is disposed on the substrate to extend along a second direction being perpendicular to the first direction. The at least one bit line comprises a plurality of pins extending toward the substrate, and each of the pins is alternately arranged with each of the isolation fins along the second direction.

Method of fabricating semiconductor device having bit line comprising a plurality of pins extending toward the substrate

A semiconductor memory device includes a substrate, at least one word line, a plurality of bit lines and a plurality of insulating structures. The word line is disposed in the substrate, extends along a first direction, and includes a gate cap layer. The bit lines are disposed on the substrate and respectively extend along a second direction. The bit line crosses the word line, and includes a conductive layer. The insulating structures are disposed on the word line and respectively disposed between the bit lines. The bottom surface of the insulating structure is located in the gate cap layer. The area of the top surface of the insulating structure is larger than the area of the bottom surface of the insulating structure.

A method for forming a semiconductor structure includes providing a substrate, forming an upper sacrificial layer, an upper supporting layer and a hard mask layer on the substrate, forming bottom electrodes through the upper sacrificial layer, the upper supporting layer and the hard mask layer, forming at least an opening between the bottom electrodes and through the hard mask layer and the upper supporting layer to partially expose the upper sacrificial layer. A portion of at least one of the bottom electrodes exposed from the opening has a slope profile, and a lower end of the slope profile is not lower than a lower surface of the upper supporting layer. The method further includes removing the upper sacrificial layer from the opening to form a cavity, and forming a capacitor dielectric layer along the bottom electrodes and a conductive material filling the cavity.

Semiconductor structure including capacitor and method for forming the same

The present disclosure relates to a semiconductor memory device including a substrate, a plurality of buried word lines, a plurality of bit lines, and a plurality isolation fins. The substrate includes a plurality of active areas and a shallow trench isolation. The buried word lines are disposed in the substrate. The bit lines are disposed on the substrate. The isolation fins are disposed on the substrate, over each of the buried word lines respectively, wherein a portion of the isolation fins is disposed under the bit lines and overlapped with the bit lines.

Growing community of inventors

Zhangzhou, China

Janbo Zhang