Vanguard International Semiconductor Corporation

Jan Mye Sung

Chih-Yuan Lu

Ing-Ruey Liaw

Ming-Hong Kuo

Howard Clayton Kirsch

A process for fabricating a DRAM cell has been developed, in which two interlaced patterns, each comprised of capacitor node contact holes and bit line contact holes, are independently created, each using a specific photolithographic mask, and a specific photolithographic procedure. The two interlaced patterns allow the creation of the capacitor node contact images, and the bit line contact holes images, to be formed in a thin polysilicon layer, with minimum spacing between contact images. Capacitor node contact holes, as well as bit line contact holes, are than formed in an insulator layer, via a dry etching procedure, using the patterned thin polysilicon layer as a mask. The use of specific masks, or of the interlaced pattern, allows the minimum spacing, between a capacitor node contact hole, and a bit line contact hole, to be limited only by the overlay between photolithographic masks.

Design and a novel process for formation of DRAM bit line and capacitor

The present invention provides a method for fabricating a multiple pillar shaped capacitor which has pillars of a smaller dimension than the resolution of the photolithography tool. The invention has two embodiments for forming the pillars and third embodiment for patterning a conductive layer into discrete bottom electrodes. The method begins by forming a conductive layer on a first planarization layer. For the first embodiment, the pillars are formed using a photolithography mask with a pattern of spaced transparent areas. The dimensions of the spaced transparent areas and distances between the spaced transparent areas are smaller that the resolution of the lithographic tool. Spaced oxide islands are formed with the mask and are used as an etch mask to form spaced pillars from the conductive layer. The second embodiment for forming the pillars involves using small titanium silicide islands as an etch mask to define the pillars. The third embodiment uses two resist layers and a photo mask shifting (offset) technique to form small spaces between the electrodes. Lastly, a capacitor dielectric layer and a top electrode are formed over the bottom electrodes thereby completing the capacitor with a pillar structure.

Method for forming a capacitor with a multiple pillar structure

A method for creating an STC structure, using a crown shaped storage node structure, to increase surface area, and to increase the capacitance, for high density, DRAM designs, has been developed. The process features creating the crown shaped, storage node structure, using only two photolithographic masking procedures. An insulator mesa is formed on an underlying polysilicon layer, to provide a shape needed for creation of polysilicon spacers, connecting to the underlying polysilicon layer. Timed, anisotropic RIE procedures, applied to the underlying polysilicon layer, and selective removal of the insulator mesa, result in the formation of the crown shaped, storage node structure, comprised of polysilicon spacers, connected to, and extending upwards, from an underlying polysilicon shape.

Method for fabricating a crown shaped capacitor structure

A DRAM cell structure, and a fabrication process to create the DRAM cell structure, has been developed. The area consumed by the DRAM cell structure is reduced by vertically aligning a polysilicon word line structure, to an underlying bit line structure, and to an overlying capacitor structure. The process features creating a narrow hole in a polysilicon word line structure, and in overlying and underlying insulator layers. The narrow hole, when filled with single crystalline silicon, connects the polysilicon word line structure to an underlying bit line structure, as well as connecting to an overlying capacitor structure.

Method of fabricating a DRAM cell with an area equal to four times the

The present invention provides a method of manufacturing a bit line for a three polysilicon layer DRAM. The method begins by providing a drain region between two spaced transfer gates on a substrate, a first silicon oxide insulation layer over the drain, a capacitor having a polysilicon top plate, the polysilicon top plate extending over the drain, and an inter metal dielectric layer over the resultant structure. First, a bit line contact opening is formed in the inter metal dielectric layer stopping at the top plate over the drain. Next, anisotropic polysilicon etch is used to remove the top plate over the drain. Third, dielectric spacers are formed on the sidewalls of the bit line opening. Fourth, the bitline opening lined by the spacers is filled with a metal to contact the bit line. The spacers insulate the plate electrode from the bit line. Also, the spacers allow a smaller bit line to be used thereby making the memory cell smaller.

Method for fabricating a bit line over a capacitor array of memory cells

The present invention provides a method of manufacturing twin wells in a silicon substrate which uses only one photo step and provides a smooth surface topology. The first embodiment begins by forming spaced field oxide regions in the substrate. The spaced field oxide regions define a first region and a second region. A masking layer composed of borophosphosilicate glass (BPSG) and a barrier layer are formed over the field oxide regions. The barrier layer and the masking layer over the first region are removed by a photo etch process. Then, N-type impurities are implanted into the first region forming a n-well using the barrier layer and masking layers as a mask. Then, p-type impurities are implanted into the substrate to form a p-type layer beneath the N-well and a P-well in the second region. The barrier layer and the masking layer are then removed. The substrate is then annealed to drive in the ion implanted impurities thereby forming a n-well and a p-well. A first embodiment uses a barrier layer formed of silicon nitride and a second embodiment uses a barrier layer formed of amorphous silicon.

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Yang Mei, Taiwan

Jan Mye Sung