Kulicke & Soffa Holdings, Inc.

Jan I Strandberg

David J Chazan

Solomon I Beilin

Michael P Skinner

Sundar M Kamath

James L Lykins

Ted T Chen

Scott M Westbrook

Todd S Kaplan

The present invention provides a solution to the problem of controlling the inter-layer impedance of a deposited thin film layer stack accommodating high-density interconnects. The invention enables high-density signal lines to be routed over a reference plane to achieve a desired characteristic impedance. In one embodiment, a first thin-film metal layer is formed on a planarized layer fabricated from multiple thin film dielectric layers. The reduced pad footprint in the first thin-film metal layer allows a major portion of the first thin-film metal layer to serve as a reference, or ground, plane to signal lines formed in a second thin-film metal layer that is separated from the first thin-film metal layer by a thin dielectric layer.

Printed wiring board with controlled line impedance

A wiring substrate with reduced thermal expansion stress. A wiring substrate, such as a laminated PWB, thin film circuit, lead frame, or chip carrier accepts an integrated circuit, such as a die, a flip chip, or ball grid array package. The wiring substrate has a thermal expansion stress reduction insert, void, or constructive void in a thermal expansion stress region proximate to the integrated circuit. The thermal expansion stress reduction insert or void may extend a selected distance from the edge or edges of the integrated circuit attachment area. The thermal expansion stress reduction insert or void improves the flexibility of the wiring substrate in the region that is joined to the integrated circuit, thus reducing thermal stress between components of the wiring substrate-integrated circuit assembly. In another embodiment, layers of a laminated wiring substrate are intentionally not bonded beneath the chip attach area, thus allowing greater flexibility of the upper layer of the laminate.

Isolated flip chip of BGA to minimize interconnect stress due to thermal mismatch

The present invention provides a method for controlling the mechanical stresses at the interfaces of the metal and dielectric materials in the printed wiring substrates of high density interconnects. The invention enables the minimization of cracking due to these stresses and does so in an economically attractive process that is able to meet the needs of today's high density interconnect applications. In one embodiment, the method of the present invention dispenses mechanical stresses in a high density interconnect printed wiring board substrate having a first patterned conductive layer formed over an upper surface of the substrate. The patterned conductive layer includes multiple conductive lines each having edges that define the boundaries of the conductive lines. The method of the invention forms a composite dielectric layer over the first patterned conductive layer and between the edges of the conductive layer. The composite dielectric layer includes particles suspended in the layer in order to reduce the likelihood and prevent any cracks that form in the layer from propagating through the entire length of the layer. A thin film conductive layer is then formed over the composite dielectric layer, and a thin film dielectric layer is formed over the thin film conductive layer. In a preferred embodiment, the composite dielectric layer is a CIBA PROBIMER&trade; layer deposited from a curtain coating process.

Deposited thin film build-up layer dimensions as a method of relieving stress in high density interconnect printed wiring board substrates

Low-impedance high density deposited-on-laminate (DONL) structures having reduced stress features reducing metallization present on the laminate printed circuit board. In this manner, reduced is the force per unit area exerted on the dielectric material disposed adjacent to the laminate material that is typically present during thermal cycling of the structure.

Low-impedance high-density deposited-on-laminate structures having reduced stress

Isolated flip chip or BGA to minimize interconnect stress due to thermal mismatch

A method for forming a high density interconnect printed wiring board substrate that has a first patterned conductive layer formed over an upper surface of the substrate that includes multiple conductive lines having edges that define the boundaries of the conductive lines and a dielectric layer formed over the patterned conductive layer and between the edges of the conductive lines. The method includes forming a thin film conductive layer over the dielectric layer, and patterning the thin film conductive layer such that, after the patterning step, the thin film conductive layer overlies each of the edges of the conductive lines. In a preferred embodiment, the thin film conductive layer is patterned such that, after the patterning step, the layer overlies the edges of the conductive lines by at least 10 microns. In another aspect of the invention, a method for strengthening thin film build-up layers deposited over a high density interconnect common circuit base is taught. According to this aspect, a photo-definable thin film dielectric layer having a coefficient of expansion of less than about 10% is formed over a patterned conductive layer, and a thin film conductive layer is formed over the photo-definable thin film dielectric layer. The thin film conductive layer is then patterned to include a plurality of signal lines and a plurality of thieving lines with the thieving lines being placed between nonuniformly spaced signal lines to provide a substantially uniform combined pattern of signal lines and thieving lines.

Method for controlling stress in thin film layers deposited over a high density interconnect common circuit base

A method for forming a planarized thin film dielectric film on a surface of a common circuit base upon which one or more integrated circuits are to be attached. The common circuit base includes raised features formed over its surface such that the raised features define a trench area between them. The method includes the steps of forming a first layer of the dielectric film over the common circuit base and over the raised features and the trench, then patterning the newly formed layer to remove portions of the layer formed over the raised features and expose the raised features. After the layer is patterned, formation of the dielectric film is completed by forming a second layer of the dielectric film over the patterned first layer. Additional film deposition and film patterning steps are performed to complete the layout of a thin film interconnect structure over said common circuit base, and an integrated circuit die is attached to the common circuit base and electrically connecting to the thin film interconnect structure. In a preferred embodiment, the first and second layers of the dielectric film are both formed from a photo-definable material and the patterning step includes exposing the first layer to light through a patterned mask corresponding to the raised features and developing the exposed layer with a developing solution to etch away portions of the first layer formed over the raised features.

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Cupertino, CA, United States of America

Jan I Strandberg