St Assembly Test Services Inc.

Sv Probe Pte. Ltd.

Flip Chip Technologies, L.l.c.

Jamin Ling

Kambhampati Ramakrishna

Dean Paul Kossives

Theodore Gerard Tessier

Diane Sahakian

Jordan Lane Wahl

Edward Lap Zak Law

Keith Heinemann

Dave Charles Stepniak

Richard McCullough

Brian McHugh

An approach is provided for fabricating probe elements for probe card assemblies. Embodiments of the invention include using a reusable substrate, a reusable substrate with layered probe elements and a reusable substrate with a passive layer made of a material that does not adhere well to probe elements formed thereon. Examples of probe elements include, without limitation, a cantilever probe element, a vertically-oriented probe element, and portions of probe elements, e.g., a beam element of a cantilever probe element. Probe elements, or portions of probe elements, may be formed using any of a number of electroforming or plating processes such as, for example, plating using masking techniques, e.g., using lithographic techniques such as photolithography, stereolithography, X-ray lithography, etc.

Approach for fabricating probe elements for probe card assemblies using a reusable substrate

An optoelectronic sensor is attached to an optically transparent substrate, such as glass, and encapsulated to form an optoelectronic device. An optical assembly can be mounted opposite the optoelectronic sensor. Filters and refractive index matching materials may be included between the optoelectronic sensor and the optically transparent substrate.

Packaging for optoelectronic devices

A nickel/palladium/gold metallization stack is formed upon connection pads of integrated circuits at the wafer level through an electroless plating method. The metallization stack can be formed over copper or aluminum interconnect pads; the lower nickel layer bonds securely to the copper or aluminum interconnect pads, while the intermediate palladium layer serves as a diffusion barrier for preventing the nickel from out-diffusing during subsequent thermal cycles. The upper gold layer adheres to the palladium and readily receives a variety of interconnect elements, including gold bumps, gold wire bonds, solder bumps, and nickel bumps. The electroless plating process permits connection pads to be formed using fine geometries, and allows adjacent connection pads to be formed within 5 micrometers of each other.

Electroless Ni/Pd/Au metallization structure for copper interconnect substrate and method therefor

Growing community of inventors

Scottsdale, AZ, United States of America

Jamin Ling