International Business Machines Corporation

Lenovo (singapore) Pte. Ltd.

Jamil A Wakil

Kamal Kumar Sikka

Michael A Gaynes

Hilton T Toy

David L Questad

Randall Joseph Stutzman

Jeffrey Thomas Coffin

Hendrik F Hamann

Harm Peter Hofstee

Vinod Kamath

Eric A Johnson

Mark Edward Steinke

James Andrew Lacey

Xiaojin Wei

Alan Weger

Michael A Boraas

Evan G Colgan

Gerald Keith Bartley

Stefano Sergio Oggioni

Robert J Von Gutfeld

David John Russell

Jeffrey Allen Zitz

Michael Raymond Miller

Sanjeev Balwant Sathe

John Harold Magerlein

Amilcar R Arvelo

Kenneth Charles Marston

Michael Sven Miller

Martin Patrick O'Boyle

David R Motschman

Jiantao Zheng

Krishna Darbha

Kathryn C Rivera

Varaprasad Venkata Calmidi

Ronald S Malfatt

Methods, apparatuses, and computer program products for forming an overmolded dual in-line memory module (DIMM) cooling structure are provided. Embodiments include identifying, by a tagging module, contextual information indicating circumstances in which the photograph was taken; based on the contextual information, selecting, by the tagging module, candidate profiles from a plurality of friend profiles associated with a profile of a user; and suggesting, by the tagging module to the user, the selected candidate profiles as potential friends to tag in the photograph.

Overmolded dual in-line memory module cooling structure

Method of forming an overmolded dual in-line memory module cooling structure

A die stack package is provided and includes a substrate, a stack of computing components, at least one thermal plate, which is thermally communicative with the stack and a lid supported on the substrate to surround the stack and the at least one thermal plate to thereby define a first heat transfer path extending from one of the computing components to the lid via the at least one thermal plate and a fin coupled to a surface of the lid and the at least one thermal plate, and a second heat transfer path extending from the one of the computing components to the lid surface without passing through the at least one thermal plate.

Enhanced thermal management of 3-D stacked die packaging

Disclosed are thermally conductive plates. Each plate is configured such that a uniform adhesive-filled gap may be achieved between the plate and a heat generating structure when the plate is bonded to the heat generating structure and subjected to a temperature within a predetermined temperature range that causes the heat generating structure to warp. Additionally, this disclosure presents the associated methods of forming the plates and of bonding the plates to a heat generating structure. In one embodiment the plate is curved and modeled to match the curved surface of a heat generating structure within the predetermined temperature range. In another embodiment the plate is a multi-layer conductive structure that is configured to undergo the same warpage under a thermal load as the heat generating structure. Thus, when the plate is bonded with the heat generating structure it is able to achieve and maintain a uniform adhesive-filled gap at any temperature.

Method of forming a flip-chip package

There is provided a method for measuring thermal properties of a semiconductor packaging material. The method includes incorporating at least one conducting feature into a substrate that includes the semiconductor packaging material, applying an electric current to the feature, and measuring a change in temperature of a region of the substrate around the feature as a result of the electric current. There is also provided a test vehicle for measuring thermal properties of a semiconductor packaging material.

Structure and method for reliability evaluation of FCPBGA substrates for high power semiconductor packaging applications

An apparatus to reduce a thermal penalty of a three-dimensional (3D) die stack for use in a computing environment is provided and includes a substrate installed within the computing environment, a first component to perform operations of the computing environment, which is coupled to the substrate in a stacking direction, a set of second components to perform operations of the computing environment, each of which is coupled to the first component and segmented with respect to one another to form a vacated region, a thermal interface material (TIM) disposed on exposed surfaces of the first and second components, and a lid, including a protrusion, coupled to the substrate to overlay the first and second components such that the protrusion extends into the vacated region and such that surfaces of the lid and the protrusion thermally communicate with the first and second components via the TIM.

Segmentation of a die stack for 3D packaging thermal management

Techniques for enhancing thermal design of a system having a number of boundary values are provided. A method for such enhancement includes representing thermal response of the system to the boundary values, obtaining at least one constraining parameter, and determining spatial and/or temporal distribution of the boundary values. The thermal response is represented as a superposition of temperature fields associated with given boundary values. The spatial and/or temporal distribution of the boundary values is determined based on the thermal response represented in the representing step, so as to satisfy the constraining parameter. The boundary values can be, for example, power sources, and the at least one constraining parameter can be, for example, a spatial or temporal location of one of the power sources.

Techniques for distributing power in electronic circuits and computer systems

Optimized thermally conductive plate and attachment method for enhanced thermal performance and reliability of flip chip organic packages

A present invention provides real-time temperature and power mapping of fully operating electronic devices. The method utilizes infrared (IR) temperature imaging, while an IR-transparent coolant flows through a specially designed cell directly over the electronic device. In order to determine the chip power distributions the individual temperature fields for each heat source of a given power and size on the chip (as realized by a scanning focused laser beam) are measured under the same cooling conditions. Then the measured chip temperature distribution is represented as a superposition of the temperature fields of these individual heat sources and the corresponding power distribution is calculated with a set of linear equations.

Method and system for measuring temperature and power distribution of a device

A chip package is provided with multiple ways of attaching a heat sink directly to the chip carrier. Corner post are mounted to the surface of the chip carrier. A heat spreading plate, with a surface area substantially the same size as the surface area of the chip carrier, is positioned in thermal contact with the surface of a flip chip, for example. The heat spreading plate has corner cuts to accommodate the corner posts of the chip carrier and notches cut into at least two opposing sides. A heat sink plate with holes extending therethrough at each of its four corners is positioned to allow the corner posts of said chip carrier to extend therethrough. Notches cut in two opposing sides of said heat sink plate are aligned with the notches in said heat spreading plate to create slots for a flexible clip to clamp the assembly together. Alternatively, nuts may also be threaded onto the posts to clamp the assembly together.

Flip chip package with heat spreader allowing multiple heat sink attachment

An electrical structure or package, and associated method of formation. A plurality of logic chips is coupled electrically to a memory chip either through conductive members (e.g., solder balls) that interface with the memory chip and each logic chip, or through a sequential logic-to-memory electrically conductive path that includes: a first conductive member electrically coupled to a logic chip; an electrically conductive via path through a circuitized substrate; and a second conductive member electrically coupled to the memory chip. The logic chips are electrically coupled to the substrate either directly through an interfacing solder interconnection from the logic chip to the substrate, or indirectly through the memory chip such that the memory chip is electrically coupled to the substrate by an interfacing solder interconnect. The electrical structure may be plugged into a socket of a backplane of a circuit card.

Packaging for multi-processor shared-memory system

A heat sink structure is formed by stacking a plurality of heat sink layers. Each layer comprises an array of vertically disposed heat dissipating elements extending from a base plate. Cut outs are formed in each of the base plates to form openings so that when the layers are stacked, each of the ascending successive layers has a larger opening than the layer upon which it rests. Cooling may be by forced air or natural convection. With forced air, air impinges on the top of the stack and into the opening in the base plates. Because of diminishing size of the openings in the stack, a portion of the air is forced out the sides of each layer. With natural convection, air is drawn into the sides of each layer and the hot air at the center flows upwardly through the openings with increasing volume as it rises.

Heat sink structure with pyramidic and base-plate cut-outs

Growing community of inventors

Austin, TX, United States of America

Jamil A Wakil