Intel Corporation

James W Conary

Jeffrey L Miller

Robert R Beutler

Michael J Allen

Jonathan H Liu

David P DiMarco

Mahadevamurty Nemani

Vijaya Bandara Wickremarachchi

John A Deetz

Embodiments of the invention provide techniques for reducing standby power consumption due to leakage currents in memory circuits. In some embodiments, systems are provided with one or more processors having) bit cells coupled to a word-line node and to a virtual ground node. The word-line node is to be at an active word-line voltage when the row is active and an inactive word-line voltage when the row is inactive. The virtual ground node is to be at an operational ground voltage when the memory array is enabled and at an elevated voltage when the memory array is in a standby mode. There is also a word-line driver circuit coupled to the bit cells through the word-line and virtual ground nodes. The current leakage in the bit cells and word-line driver circuit is reduced during the standby mode when the virtual ground node is at the elevated voltage.

Memory array leakage reduction circuit and method

Disclosed herein are techniques for reducing standby power consumption due to leakage currents in memory array circuits.

An input buffer circuit includes an input buffer. The input buffer has an input adapted to be coupled to an address bus and a power down input. The input buffer circuit further includes power down circuitry adapted to be coupled to an address bus strobe and coupled to the power down input. When the address bus is detected to be idle by the power down circuitry, a power down signal is sent to the power down input. This powers down the input buffer.

Input buffer circuit with dual power down functions

A time delay from a triggering event to switching of an output signal in a microelectronic device can be adjusted to compensate for various characteristics of the electronic device. The characteristics include temperature, voltage, and manufacturing process conditions. The time delay is adjusted using a variable delay circuit having multiple delay cells that are selectively coupled to control the time delay. The conditions of the electronic device are detected using a process sensor, which includes an oscillator having a frequency that is sensitive to variations in the conditions.

Detecting states of signals

Reducing timing variance of signals from an electronic device

Method and apparatus to monitor a characteristic associated with an electronic device

A synchronous interface to a self-timed memory array includes one or more address bus inputs and a first latch stage that includes one or more latches. Each of the latches of the first latch stage includes an input coupled to one of the address bus inputs and a first output. The synchronous interface further includes a second latch stage that includes a plurality of latches. Each of the latches of the second latch stage includes an input coupled to one of the first outputs of the first latch stage and a second output coupled to the memory array.

Synchronous interface to a self-timed memory array

A method and apparatus for reducing the power consumption of an integrated circuit when the core logic of the integrated circuit is in the quiescent or idle state. The method and apparatus includes a phase locked loop (PLL) circuit for generating an internal clock, wherein the frequency of the internal clock is at a predetermined multiple of the frequency of the global clock signal. When the integrated circuit is quiescent, the present invention provides circuitry which permits the internal clock to be slowed to a lower frequency or the internal clock to be frozen to reduce power consumption.

Method and apparatus for powering down an integrated circuit having a

A microprocessor that operates at the speed of the the bus or at a speed which is a multiple of the bus speed-on a selectable basis. The microprocessor includes a phase locked loop to generate clock signals for operations within the microprocessor and bus clock signals for data transfer operations on the bus. The present invention allows a microprocessor core to operate at the same frequency or twice the frequency of the address/data buses.

Integrated circuit having a core which operates at a speed greater than

A method and apparatus for powering down a microprocessor in a computer system. The method and apparatus includes a phase locked loop (PLL) circuit, wherein the phase locked loop generates bus clock signals for clocking the operations on the bus and core clock signals for clocking the core of the processor in response to global clock signal of the computer system. The microprocessor includes circuitry for processing data synchronous with the core clock signals. The method and circuit also includes circuitry for placing the processor in a reduced power consumption state in response to the execution of a power down instruction. In this manner, the computer system reduces power consumption.

Method and apparatus for powering down an integrated circuit

A microprocessor that operates at the speed of the the bus or at a speed which is a multiple of the bus speed on a selectable basis. The microprocessor includes a phase locked loop to generate clock signals for operations within the microprocessor and bus clock signals for data transfer operations on the bus. The present invention allows a microprocessor core to operate at the same frequency or twice the frequency of the address/data buses.

Apparatus for operating a microprocessor core and bus controller at a

A method and apparatus for allowing a processor to invalidate an individual line of its internal cache while in a non-clocked low power state. The present invention includes circuitry for placing the processor in a reduced power consumption state. The present invention also includes circuitry for powering up the processor out of the reduced power consumption state to invalidate data in the cache in order to maintain cache coherency while in the reduced power consumption state.

Method and apparatus for invalidating a cache while in a low power state

A circuit and method in a computer system for generating a power-up reset pulse is disclosed. A specially designed flip-flop and a voltage shifter create a signal that ramps-up with a rising voltage from a newly activated power supply until a desired voltage level is reached. The signal is then deasserted and, in one embodiment, the circuit is reset so that another reset signal can be generated should power be removed and then reapplied in a short period of time. This circuit is configured so that no DC current paths from power to ground exist within the circuit once the reset pulse generation is complete.

Zero standby current power-up reset circuit

A microprocessor that operates at the speed of the bus or at a speed which is a multiple of the bus speed on a selectable basis. The microprocessor includes a phase locked loop to generate clock signals to clock the operations within the microprocessor and bus clock signals to clock data transfer operations between the microprocessor and the bus.

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Aloha, OR, United States of America

James W Conary