International Business Machines Corporation

Globalfoundries Inc.

Globalfoundries U.S. 2 LLC

James Stuart Dunn

David Louis Harame

Stephen Arthur St Onge

Qizhi Liu

Alvin Jose Joseph

Anthony K Stamper

Douglas Duane Coolbaugh

Louis DeWolf Lanzerotti

Zhong-Xiang He

Jeffrey Bowman Johnson

Robb Allen Johnson

Ryan Wayne Wuthrich

Steven J Holmes

Steven H Voldman

Robert K Leidy

Kathryn Turner Schonenberg

Jack Oon Chu

Jeffrey Scott Brown

Renata A Camillo-Castillo

Alan Bernard Botula

Andreas Daniel Stricker

David R Greenberg

Basanth Jagannathan

Nicholas Theodore Schmidt

Kenneth Knetch Kieft, Iii

David V Horak

David Charles Sheridan

Peter B Gray

Peter John Geiss

Douglas Brian Hershberger

Michael D Gordon

Blaine Jeffrey Gross

Jeffrey P Gambino

Edmund Juris Sprogis

Robert Mark Rassel

Marwan H Khater

James Albert Slinkman

Edward Crandal Cooney, Iii

James Spiros Nakos

Cornelia K Tsang

Leathen Shi

Natalie Barbara Feilchenfeld

Peter James Lindgren

Francois Pagette

Cuc Kim Huynh

BethAnn Rainey

Dale Warner Martin

Eric Adler

Charles S Musante

Marc Waine Cantell

Robert Andrew Kertis

Peng Cheng

Paul William Pastel

Dinh Dang

Brian L Tessier

Eric D Johnson

Kent E Morrett

Mark E Stidham

Mohamed Youssef Hammad

Albert Edson Lanpher

Michael Dean Hulvey

Edward J Nowak

Edith H Stern

Barry Edward Willner

James William Adkisson

Shreesh Narasimha

John Joseph Pekarik

Joseph Andrew Iadanza

Anthony I Chou

Christopher Stephen Putnam

Seshadri Subbanna

Josef S Watts

Christopher M Schnabel

Jenifer E Lary

Bruce P Semple

Mohammed Y Hammad

Douglass Duane Coolbaugh

Jeffery S Brown

BethAnn Rainey Lawrence

Brian M Dufrene

Christopher H Lumbra

Structures and methods of making a dielectric region in a bulk silicon (Si) substrate of a mixed-signal integrated circuit (IC) provide a high-Q passive resonator. Deep trenches within the bulk Si substrate in &#x3c;100&#x3e; directions are expanded by wet etching to form contiguous cavities, which are filled by Si oxide to form a dielectric region. The dielectric region enhances the quality (Q) of an overlying passive resonator, formed in metallization layers of the mixed-signal IC.

Dielectric region in a bulk silicon substrate providing a high-Q passive resonator

Various embodiments include field effect transistors (FETs) and methods of forming such FETs. One method includes: forming a first set of openings in a precursor structure having: a silicon substrate having a crystal direction, the silicon substrate substantially abutted by a first oxide; a silicon germanium (SiGe) layer overlying the silicon substrate; a silicon layer overlying the SiGe layer; a second oxide overlying the silicon layer; and a sacrificial layer overlying the second oxide, wherein the first set of openings each expose the silicon substrate; undercut etching the silicon substrate in a direction perpendicular to the crystal direction of the silicon substrate to form a trench corresponding with each of the first set of openings; passivating exposed surfaces of at least one of the SiGe layer or the silicon layer in the first set of openings; and at least partially filling each trench with a dielectric.

Single-chip field effect transistor (FET) switch with silicon germanium (SiGe) power amplifier and methods of forming

Various embodiments include field effect transistors (FETs) and related integrated circuit (IC) layouts. One FET includes: a silicon substrate including a set of trenches; a first oxide abutting the silicon substrate; a silicon germanium (SiGe) layer overlying the silicon substrate; a silicon layer overlying the SiGe layer; a second oxide overlying the silicon layer, wherein the silicon layer includes a plurality of salicide regions; a gate structure overlying the second oxide between adjacent salicide regions; and a first contact contacting the gate structure; a second contact contacting one of the salicide regions; a third oxide partially filling the set of trenches and extending above the silicon layer overlying the SiGe layer; and an air gap in each of the set of trenches, the air gap surrounded by the third oxide.

A high density capacitor and low density capacitor simultaneously formed on a single wafer and a method of manufacture is provided. The method includes depositing a bottom plate on a dielectric material; depositing a low-k dielectric on the bottom plate; depositing a high-k dielectric on the low-k dielectric and the bottom plate; depositing a top plate on the high-k dielectric; and etching a portion of the bottom plate and the high-k dielectric to form a first metal-insulator-metal (MIM) capacitor having a dielectric stack with a first thickness and a second MIM capacitor having a dielectric stack with a second thickness different than the first thickness.

Complimentary metal-insulator-metal (MIM) capacitors and method of manufacture

Methods for bonding substrate surfaces, bonded substrate assemblies, and design structures for a bonded substrate assembly. Device structures of a product chip are formed using a first surface of a device substrate. A wiring layer of an interconnect structure for the device structures is formed on the product chip. The wiring layer is planarized. A temporary handle wafer is removably bonded to the planarized wiring layer. In response to removably bonding the temporary handle wafer to the planarized first wiring layer, a second surface of the device substrate, which is opposite to the first surface, is bonded to a final handle substrate. The temporary handle wafer is then removed from the assembly.

Flattened substrate surface for substrate bonding

Method for making a dielectric region in a bulk silicon substrate providing a high-Q passive resonator

At least one isolation trench formed in a layer stack including substrate, channel, and upper gate layers define a channel in the channel layer. Lateral etching from the isolation trench(es) can form lateral cavities in the substrate and upper gate layer to substantially simultaneously form self-aligned lower and upper gates. The lower gate undercuts the channel, the upper gate is narrower than the channel, and a source and a drain can be formed on opposed ends of the channel. As a result, source-drain capacitance and gate-drain capacitance can be reduced, increasing speed of the resulting FET.

Field effect transistor (FET) with self-aligned double gates on bulk silicon substrate, methods of forming, and related design structures

Device structures and design structures for a bipolar junction transistor. A first isolation structure is formed in a substrate to define a boundary for a device region. A collector is formed in the device region, and a second isolation structure is formed in the device region. The second isolation structure defines a boundary for the collector. The second isolation structure is laterally positioned relative to the first isolation structure to define a section of the device region between the first and second isolation structures.

Trench isolation for bipolar junction transistors in BiCMOS technology

According to a bipolar transistor structure having a transistor top and a transistor bottom herein, a silicon substrate located at the transistor bottom has a collector region of a first conductivity type. An epitaxial base layer of a second conductivity type overlies, relative to the transistor top and bottom, a portion of the collector region. The epitaxial base layer has a bottom surface on the silicon substrate and a top surface opposite the bottom surface. A top region, relative to the transistor top and bottom, of the epitaxial base layer comprises a concentration of germanium having atomic compositions sufficient to avoid impacting transistor parameters, and sufficient to be resistant to selective chemical etching. A silicon emitter layer of the first conductivity type overlies, relative to the transistor top and bottom, a portion of the epitaxial base layer adjacent to the top surface of the epitaxial base layer.

Base profile of self-aligned bipolar transistors for power amplifier applications

A substrate includes a first region having a first resistivity, for optimizing a field effect transistor, a second region having a second resistivity, for optimizing an npn subcollector of a bipolar transistor device and triple well, a third region having a third resistivity, with a high resistivity for a passive device, a fourth region, substantially without implantation, to provide low perimeter capacitance for devices.

Forming structures on resistive substrates

Device structures, fabrication methods, and design structures for a bipolar junction transistor. A first isolation structure is formed in a substrate to define a boundary for a device region. A collector is formed in the device region, and a second isolation structure is formed in the device region. The second isolation structure defines a boundary for the collector. The second isolation structure is laterally positioned relative to the first isolation structure to define a section of the device region between the first and second isolation structures.

A method of forming an integrated circuit structure includes: forming a vent via extending through a shallow trench isolation (STI) and into a substrate; selectively removing an exposed portion of the substrate at a bottom of the vent via to form an opening within the substrate, wherein the opening within the substrate abuts at least one of a bottom surface or a sidewall of the STI; and sealing the vent via to form an air gap in the opening within the substrate.

Integrated circuit structure having air-gap trench isolation and related design structure

A low capacitance density, high voltage MIM capacitor and the high density MIM capacitor and a method of manufacture are provided. The method includes depositing a plurality of plates and a plurality of dielectric layers interleaved with one another. The method further includes etching a portion of an uppermost plate of the plurality of plates while protecting other portions of the uppermost plate. The protected other portions of the uppermost plate forms a top plate of a first metal-insulator-metal (MIM) capacitor and the etching exposes a top plate of a second MIM capacitor.

Method of manufacturing complimentary metal-insulator-metal (MIM) capacitors

Growing community of inventors

Jericho, VT, United States of America

James Stuart Dunn