International Business Machines Corporation

Globalfoundries Inc.

Globalfoundries U.S. 2 LLC

James Spiros Nakos

Steven M Shank

Jay Sanford Burnham

Timothy Wayne Kemerer

James J Quinlivan

Anthony K Stamper

Chung H Lam

John J Ellis-Monaghan

Mark Charles Hakey

Cyril Cabral, Jr

Randy William Mann

William Joseph Murphy

Jenifer E Lary

Beth A Ward

Clement Hsingjen Wann

Terence B Hook

Arne Watson Ballantine

Zhijiong Luo

Christian Lavoie

Jeffrey Bowman Johnson

Richard Quimby Williams

Stephen Ellinwood Luce

Eric Jeffrey White

Sunfei Fang

An L Steegen

John Anthony Bracchitta

James Randall Elliott

Chester T Dziobkowski

Scott Alan Estes

Nicholas Mone, Jr

Tushar Desai

Ellis Craig Hayford

Joseph Kerry Vaughn Comeau

Leslie Peter Crane

Alan Michael Chandler

Lawrence Alfred Clevenger

Steven J Holmes

Toshiharu Furukawa

Charles W Koburger, Iii

Jed Hickory Rankin

Qizhi Liu

Katherine Lynn Saenger

Kirk David Peterson

Douglas Duane Coolbaugh

Edmund Juris Sprogis

Robert Mark Rassel

Xuefeng Liu

James Stuart Dunn

Robert Allen Groves

Donald M Kenney

Jerome Brett Lasky

Harold G Linde

Peter James Lindgren

David Charles Sheridan

Ronnen Andrew Roy

Jonathan Daniel Chapple-Sokol

Eric Adler

Jennifer L Lund

Glen L Miles

Michael James Lercel

Michael B Rice

Deborah A Tucker

Brian M Czabaj

Francois M d'Heurle

James V Hart, Iii

Jeffrey P Gambino

David V Horak

Daniel C Edelstein

Tak H Ning

John Atkinson Fifield

Alvin Jose Joseph

Kenneth Parker Rodbell

John Joseph Pekarik

Evgeni Petrovich Gousev

Robert C Wong

Anthony I Chou

Jason D Hibbeler

Nivo Rovedo

Joseph Francis Shepard, Jr

Paul A Rabidoux

James M Harper

Ronald Dennis Rose

Bruce Walter Porth

Peter A Burke

James Allan Bruce

Peter John Geiss

Bradley Alan Orner

Paul E Bakeman, Jr

Larry Wissel

Matthew D Moon

James McKell Edwin Harper

Stephen Frank Geissler

Paul William Pastel

Henry H K Tang

Margaret L Gibson

John H Givens

Dale P Hallock

Edward D Adams

Eric Seung Lee

Brett A Philips

A method is provided to convert commercial microprocessors to radiation-hardened processors and, more particularly, a method is provided to modify a commercial microprocessor for radiation hardened applications with minimal changes to the technology, design, device, and process base so as to facilitate a rapid transition for such radiation hardened applications. The method is implemented in a computing infrastructure and includes evaluating a probability that one or more components of an existing commercial design will be affected by a single event upset (SEU). The method further includes replacing the one or more components with a component immune to the SEU to create a final device.

Method for conversion of commercial microprocessor to radiation-hardened processor and resulting processor

Solutions for forming a silicided deep trench decoupling capacitor are disclosed. In one aspect, a method of forming a semiconductor device includes: forming an outer trench in a silicon substrate, the forming exposing portions of the silicon substrate below an upper surface of the silicon substrate; depositing a dielectric liner layer inside the trench; depositing a doped polysilicon layer over the dielectric liner layer, the doped polysilicon layer forming an inner trench in the silicon substrate; forming a silicide layer over a portion of the doped polysilicon layer; forming an intermediate contact layer within the inner trench; and forming a contact over a portion of the intermediate contact layer and a portion of the silicide layer.

Deep trench decoupling capacitor and methods of forming

According to a bipolar transistor structure having a transistor top and a transistor bottom herein, a silicon substrate located at the transistor bottom has a collector region of a first conductivity type. An epitaxial base layer of a second conductivity type overlies, relative to the transistor top and bottom, a portion of the collector region. The epitaxial base layer has a bottom surface on the silicon substrate and a top surface opposite the bottom surface. A top region, relative to the transistor top and bottom, of the epitaxial base layer comprises a concentration of germanium having atomic compositions sufficient to avoid impacting transistor parameters, and sufficient to be resistant to selective chemical etching. A silicon emitter layer of the first conductivity type overlies, relative to the transistor top and bottom, a portion of the epitaxial base layer adjacent to the top surface of the epitaxial base layer.

Base profile of self-aligned bipolar transistors for power amplifier applications

A trench contact silicide is formed on an inner wall of a contact trench that reaches to a buried conductive layer in a semiconductor substrate to reduce parasitic resistance of a reachthrough structure. The trench contact silicide is formed at the bottom, on the sidewalls of the trench, and on a portion of the top surface of the semiconductor substrate. The trench is subsequently filled with a middle-of-line (MOL) dielectric. A contact via may be formed on the trench contact silicide. The trench contact silicide may be formed through a single silicidation reaction with a metal layer or through multiple silicidation reactions with multiple metal layers.

Silicided trench contact to buried conductive layer

Device structures, fabrication methods, and design structures for a capacitor of a memory cell of ferroelectric random access memory device. The capacitor may include a first electrode comprised of a first conductor, a ferroelectric layer on the first electrode, a second electrode on the ferroelectric layer, and a cap layer on an upper surface of the second electrode. The second electrode may be comprised of a second conductor, and the cap layer may have a composition that is free of titanium. The second electrode may be formed by etching a layer of a material formed on a layer of the second conductor to define a hardmask and then modifying the remaining portion of that material in the hardmask to have a comparatively less etch rate, when exposed to a chlorine-based reactive ion etch chemistry, than when initially formed.

Ferroelectric random access memory with optimized hardmask

A resistor and capacitor are provided in respective shallow trench isolation structures. The method includes forming a first and second trench in a substrate and forming a first insulator layer within the first and second trench. The method includes forming a first electrode material within the first and second trench, on the first insulator layer, and forming a second insulator layer within the first and second trench and on the first electrode material. The method includes forming a second electrode material within the first and second trench, on the second insulator layer. The second electrode material pinches off the second trench. The method includes removing a portion of the second electrode material and the second insulator layer at a bottom portion of the first trench, and filling in the first trench with additional second electrode material. The additional second electrode material is in electrical contact with the first electrode material.

Dual contact trench resistor and capacitor in shallow trench isolation (STI) and methods of manufacture

A method of fabricating a gate dielectric layer. The method includes: providing a substrate; forming a silicon dioxide layer on a top surface of the substrate; performing a plasma nitridation in a reducing atmosphere to convert the silicon dioxide layer into a silicon oxynitride layer. The dielectric layer so formed may be used in the fabrication of MOSFETs.

Method for fabricating a nitrided silicon-oxide gate dielectric

A method for forming a hydrogen barrier liner for a ferro-electric random access memory chip including forming a first dielectric layer over a substrate; forming a gate over the first dielectric layer; forming a first aluminum oxide layer over the gate and the first dielectric layer; forming a second dielectric layer over the first aluminum oxide layer; etching a trench through the second dielectric layer and the first aluminum oxide layer to the gate; forming a hydrogen barrier liner over the second dielectric layer, the hydrogen barrier liner lining the trench and contacting the gate; forming a silicon dioxide layer over the first aluminum dioxide layer, the silicon dioxide layer substantially filling the trench; and substantially removing the silicon dioxide layer leaving a silicon dioxide plug in the trench.

Hydrogen barrier liner for ferro-electric random access memory (FRAM) chip

The invention relates to a semiconductor structures and methods of manufacture and, more particularly, to a dual contact trench resistor in shallow trench isolation (STI) and methods of manufacture. In a first aspect of the invention, a method comprises forming a trench in a substrate; forming a first insulator layer within the trench; forming a first electrode within the trench, on the first insulator layer, and isolated from the substrate by the first insulator layer; forming a second insulator layer within the trench and on the first electrode; and forming a second electrode within the trench, on the second insulator layer, and isolated from the substrate by the first insulator layer and the second insulator layer.

Dual contact trench resistor in shallow trench isolation (STI) and methods of manufacture

Solutions for forming a silicided deep trench decoupling capacitor are disclosed. In one aspect, a semiconductor structure includes a trench capacitor within a silicon substrate, the trench capacitor including: an outer trench extending into the silicon substrate; a dielectric liner layer in contact with the outer trench; a doped polysilicon layer over the dielectric liner layer, the doped polysilicon layer forming an inner trench within the outer trench; and a silicide layer over a portion of the doped polysilicon layer, the silicide layer separating at least a portion of the contact from at least a portion of the doped polysilicon layer; and a contact having a lower surface abutting the trench capacitor, a portion of the lower surface not abutting the silicide layer.

Deep trench decoupling capacitor

Ferro-electric capacitor modules, methods of manufacture and design structures. The method of manufacturing the ferro-electric capacitor includes forming a barrier layer on an insulator layer of a CMOS structure. The method further includes forming a top plate and a bottom plate over the barrier layer. The method further includes forming a ferro-electric material between the top plate and the bottom plate. The method further includes encapsulating the barrier layer, top plate, bottom plate and ferro-electric material with an encapsulating material. The method further includes forming contacts to the top plate and bottom plate, through the encapsulating material. At least the contact to the top plate and a contact to a diffusion of the CMOS structure are in electrical connection through a common wire.

Ferro-electric capacitor modules, methods of manufacture and design structures

Trench capacitors and methods of manufacturing the trench capacitors are provided. The trench capacitors are very dense series capacitor structures with independent electrode contacts. In the method, a series of capacitors are formed by forming a plurality of insulator layers and a plurality of electrodes in a trench structure, where each electrode is formed in an alternating manner with each insulator layer. The method further includes planarizing the electrodes to form contact regions for a plurality of capacitors.

Embedded series deep trench capacitors and methods of manufacture

A ferro-electric random access memory (FRAM) chip, including a substrate; a first dielectric layer over the substrate; a gate over the first dielectric layer; a first aluminum oxide layer over the first dielectric layer and the gate; a second dielectric layer over the first aluminum oxide layer; a trench through the second dielectric layer and the first aluminum oxide layer to the gate; a hydrogen barrier liner over the second dielectric layer and lining the trench, and contacting the gate; and a silicon dioxide plug over the hydrogen barrier liner substantially filling the trench.

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Essex Junction, VT, United States of America

James Spiros Nakos