Irvine Sensors Corporation

Isc8 Inc.

Pfg IP LLC

Other

Aprolase Development Co., LLC

Iscs Inc.

James S Yamaguchi

Angel Antonio Pepe

W Eric Boyd

Andrew N Camien

Volkan H Ozguz

Randy Bindrup

John F Leon

David E Ludwig

Douglas Marice Albert

Peter Lieu

Ludwig David

Stuart Clark

Stewart Clark

A stackable integrated circuit chip layer and module device that avoids the use of electrically conductive elements on the external surfaces of a layer containing an integrated circuit die by taking advantage of conventional wire bonding equipment to provide an electrically conductive path defined by a wire bond segment that is encapsulated in a potting material so as to define an electrically conductive wire bond 'through-via' accessible from at least the lower or second surface of the layer.

Wire bond through-via structure and method

A method for electrically coupling an anti-tamper mesh to an electronic module or device using wire bonding equipment and a device made from the method. Stud bumps or free air ball bonds are electrically coupled to conductive mesh pads of an anti-tamper mesh. Respective module pads have a conductive epoxy disposed thereon for the receiving of the stud bumps or free air ball bonds, each of which are aligned and bonded together to electrically couple the anti-tamper mesh to predetermined module pads.

Anti-tamper wrapper interconnect method and a device

A method for defining an electrically conductive metalized structure, which may comprise an electrode or trace, on the surface of a three-dimensional element. The three-dimensional element may comprise a glass microsphere or shell resonator. A laser direct write grayscale photolithographic process is used in conjunction with electrically conductive metal deposition processes to define one or more electrically conductive metal structures on the surfaces of the three dimensional element.

Method for defining an electrically conductive metal structure on a three-dimensional element and a device made from the method

A method for fabricating a stackable integrated circuit layer and a device made from the method are disclosed. A stud bump is defined on the contact pad of an integrated circuit die and the stud-bumped die encapsulated in a potting material to define a potted assembly. A predetermined portion of the potting material is removed whereby a portion of the stud bump is exposed. One or more electrically conductive traces are defined on the layer surface and in electrical connection with the stud bump to reroute the integrated circuit contacts to predetermined locations on the layer to provide a stackable neolayer.

Method for fabricating a neo-layer using stud bumped bare die

A preprocessed semiconductor substrate such as a wafer is provided with a metal etch mask which defines singulation channels on the substrate surface. An isotropic etch process is used to define a singulation channel with a first depth extending into the semiconductor substrate material. A second anisotropic etch process is used to increase the depth of the singulation channel while providing substantially vertical singulation channel sidewalls. The singulation channel can be extended through the depth of the substrate or, in an alternative embodiment, a predetermined portion of the inactive surface of the substrate removed to expose the singulation channels. In this manner, semiconductor die can be precisely singulated from a wafer while maintaining vertical die sidewalls.

Method for precision integrated circuit die singulation using differential etch rates

A stackable layer and stacked multilayer module are disclosed. Individual integrated circuit die are tested and processed at the wafer level to create vertical area interconnect vias for the routing of electrical signals from the active surface of the die to the inactive surface. Vias are formed at predefined locations on each die on the wafer at the reticle level using a series of semiconductor processing steps. The wafer is passivated and the vias are filled with a conductive material. The bond pads on the die are exposed and a metallization reroute from the user-selected bond pads and vias is applied. The wafer is then segmented to form thin, stackable layers that can be stacked and vertically electrically interconnected using the conductive vias, forming high-density electronic modules which may, in turn, be further stacked and interconnected to form larger more complex stacks.

Stackable semiconductor chip layer comprising prefabricated trench interconnect vias

A pre-formed integrated circuit chip-containing module formed from layers is disclosed. Each layer contains an integrated circuit chip that is encapsulated into an electronic package, by forming an interconnect assembly separately from the pre-formed integrated circuit chip. If the interconnect assembly tests good it is bonded to the prepared integrated circuit chip. The interconnect assembly is flip bonded to the chip. The interconnect assembly and chip are passivated or potted into an integral structure to provide the electronic package. At least one test pad is defined in an interconnect layer, which test pad can be accessed and electrically connected on opposing sides of the test pad. The chip is underfilled with an insulating material to remove all voids between the chip and the interconnect assembly. The integrated circuit chip is then thinned. The test pad is accessed to test the chip. A plurality of interconnect assemblies and chips are bonded together to form a corresponding plurality of electronic packages. Each layer is bonded to form a stack of integrated circuit containing layers.

Three-dimensional module comprised of layers containing IC chips with overlying interconnect layers

A method is disclosed for providing electrical connections to electronic elements within a multilayer module. The method includes providing first and second active layers having first and second edges, respectively. Each active layer includes a flexible, polymer substrate and at least one electronic element formed within the substrate. Electrically-conductive traces provide electrical connections from the first and second edges to the electronic elements. An adhesive is applied to at least one of a top surface of the first active layer and a bottom surface of the second active layer and the top surface of the first active layer is adhered to the bottom surface of the second active layer. The first edge and the second edge are aligned with each other thereby forming a side of the multilayer module. Electrically-conductive lines are applied along the side of the multilayer module to provide electrical connections to the traces.

Process of manufacturing multilayer modules

A pre-formed integrated circuit chip is encapsulated into an electronic package, by forming an interconnect assembly separately from the pre-formed integrated circuit chip. If the interconnect assembly tests good it is bonded to the prepared integrated circuit chip. The interconnect assembly is flip bonded to the chip. The interconnect assembly and chip are passivated or potted into an integral structure to provide the electronic package. At least one test pad is defined in an interconnect layer, which test pad can be accessed and electrically connected on opposing sides of the test pad. The chip is underfilled with an insulating material to remove all voids between the chip and the interconnect assembly. The integrated circuit chip is then thinned. The test pad is accessed to test the chip. A plurality of interconnect assemblies and chips are bonded together to form a corresponding plurality of electronic packages.

Method of making stackable layers containing encapsulated integrated circuit chips with one or more overlaying interconnect layers

Stackable layers containing encapsulated integrated circuit chips with one or more overlying interconnect layers

A multilayer module includes a first active layer with a first edge and second active layer with a second edge. Each active layer includes a flexible, polymer substrate, at least one electronic element, and a plurality of electrically-conductive traces which provide electrical connection from the respective edge to the electronic element of the active layer. The second active layer is adhered to the first active layer so that the first edge and second edge are aligned with each other thereby forming a side of the multilayer module. The multilayer module further includes a plurality of electrically-conductive lines along the side of the multilayer module, the lines providing electrical connection to the traces.

Multilayer modules with flexible substrates

Each multilayer module of a plurality of multilayer modules has a plurality of layers wherein each layer has a substrate therein. The plurality of multilayer modules includes a first multilayer module including a first layer and a second multilayer module including a second layer each having a top side and bottom side. The first layer and second layer each includes a substrate, at least one electronic element, and a plurality of electrically-conductive traces. The plurality of multilayer modules further includes a heat-separating layer disposed between the top side of the first layer and the bottom side of the second layer. The first multilayer module is adhered to the second multilayer module and the first multilayer module can be detached from the second multilayer module by applying heat to the heat-separating layer.

Stacking of multilayer modules

A stack of multilayer modules has a segmentation layer disposed between neighboring multilayer modules. The segmentation layer facilitates the separation of neighboring multilayer modules. The stack of multilayer modules includes a first multilayer module and a second multilayer module. Each multilayer module includes a plurality of active layers each comprising a substrate, at least one electronic element, and a plurality of electrically-conductive traces. The second multilayer module is disposed to be neighboring the first multilayer module with at least one segmentation layer between the first and second multilayer modules. The segmentation layer includes a metal layer and at least one thermoplastic adhesive layer. When heat is applied, the metal layer conducts heat to the thermoplastic adhesive layer.

Growing community of inventors

Laguna Niguel, CA, United States of America

James S Yamaguchi