Tau-metrix, Inc.

Credence Systems Corporation

Dcg Systems Gmbh

Fei Efa, Inc.

Optonics, Inc.

Fei Comapny

Optonics, Inc. (a Credence Company)

James S Vickers

Nader Pakdaman

Majid Aghababazadeh

Gary L Steinbrueck

Jose J Estabil

Keith Serrels

Thomas Wong

Derryck Telford Reid

Daniel Murdoch Cotton

Praveen Vedagarbha

Mario M Pelella

Prasad Sabbineni

Thomas R Gockel

Cecelia Anne Campochiaro

Yakov Bobrov

Seema Somani

Radu Ispasoiu

Nadar Pakdaman

Described herein are a system and method of preparing integrated circuits (ICs) so that the ICs remain electrically active and can have their active circuitry probed for diagnostic and characterization purposes using charged particle beams. The system employs an infrared camera capable of looking through the silicon substrate of the ICs to image electrical circuits therein, a focused ion beam system that can both image the IC and selectively remove substrate material from the IC, a scanning electron microscope that can both image structures on the IC and measure voltage contrast signals from active circuits on the IC, and a means of extracting heat generated by the active IC. The method uses the system to identify the region of the IC to be probed, and to selectively remove all substrate material over the region to be probed using ion bombardment, and further identifies endpoint detection means of milling to the required depth so as to observe electrical states and waveforms on the active IC.

System and method of preparing integrated circuits for backside probing using charged particle beams

A pulsed-laser LADA system is provided, which utilizes temporal resolution to enhance spatial resolution. The system is capable of resolving CMOS pairs within the illumination spot using synchronization of laser pulses with the DUT clock. The system can be implemented using laser wavelength having photon energy above the silicon bandgap so as to perform single-photon LADA or wavelength having photon energy below the silicon bandgap so as to generate two-photon LADA. The timing of the laser pulses can be adjusted using two feedback loops tied to the clock signal of an ATE, or by adjusting the ATE's clock signal with reference to a fixed-pulse laser source.

Laser-assisted device alteration using synchronized laser pulses

An apparatus and method for laser voltage testing of a DUT is disclosed. The system enables laser voltage probing and laser voltage imaging of devices within the DUT. A selected area of the DUT is illuminating a while the DUT is receiving test signals causing certain of the active devices to modulate. Light reflected from the DUT is collected and is converted into an electrical signal. The electrical signal is sampled by an ADC and the output of the ADC is sent to an FPGA. The FPGA operates on the signal so as to provide an output that emulates a spectrum analyzer or a vector analyzer.

Systems and method for laser voltage imaging

A method of obtaining two orthogonally polarized super-resolution images is provided. A first diffraction-limited image is obtained using horizontally polarized light; a second diffraction-limited image is obtained using vertically polarized light; and, the first and second images are processed so as to yield a convoluted image having super diffraction-limited performance in both dimensions. Enhanced alignment of CAD image to acquired image is facilitated using the horizontally and vertically polarized images.

Apparatus and method for polarization diversity imaging and alignment

A substrate section that is at least partially fabricated to include contact elements and materials. The substrate section includes doped regions that have a heavily doped N-type region and a heavily doped P-type region adjacent to one another. An exterior surface of the substrate has a topography that includes a light-transparent region in which light, from a light source, is able to reach a surface of the substrate. An application of light onto the light transparent region is sufficient to cause a voltage potential to form across a junction of the heavily doped regions. The substrate section may further comprise one or more electrical contacts, positioned on the substrate section to conduct current, resulting from the voltage potential created with application of light onto the light transparent region, to a circuit on the semiconductor substrate.

Integrated photodiode for semiconductor substrates

The fabrication of the wafer may be analyzed starting from when the wafer is in a partially fabricated state. The value of a specified performance parameter may be determined at a plurality of test structures located on an active area of a die of the wafer. The specified performance parameter is known to be indicative of a particular fabrication process in the fabrication. Evaluation information may then be obtained based on a variance of the value of the performance parameter at the plurality of locations. This may be done without affecting a usability of a chip that is created from the die. The evaluation information may be used to evaluate how one or more processes that include the particular fabrication process that was indicated by the performance parameter value was performed.

Test structures for evaluating a fabrication of a die or a wafer

The fabrication of the wafer may be analyzed starting from when the wafer is in a partially fabricated state. The value of a specified performance parameter may be determined at a plurality of locations on an active area of a die of the wafer. The specified performance parameter is known to be indicative of a particular fabrication process in the fabrication. Evaluation information may then be obtained based on a variance of the value of the performance parameter at the plurality of locations. This may be done without affecting a usability of a chip that is created from the die. The evaluation information may be used to evaluate how one or more processes that include the particular fabrication process that was indicated by the performance parameter value was performed.

System and apparatus for using test structures inside of a chip during the fabrication of the chip

A system is provided for using test structures to evaluate a fabrication of a wafer. The test structures include a combination of device and interconnect elements that are provided on an active region of a die, on the wafer prior to the fabrication of the wafer being completed. The combination of device and interconnect elements include one or more circuits that are activatable to produce an output corresponding to measurable electrical and/or optical characteristics. A power receiving element that is configured to receive activation energy sufficient to cause the output on a contactless medium, so that the activation energy is received without affecting a usability of the die or wafer. The one or more circuits are structured to generate a variation in either the output or in a parameter determined from output, as a result of a process variation in a specific fabrication step that provided elements for forming the one or more circuits. A detector is provided to detect the output over the contactless medium, so as to receive the output without affecting a usability of the wafer when fabrication is completed.

System for using test structures to evaluate a fabrication of a wafer

Intra-chip power and test signal generation for use with test structures on wafers

A bi-convex solid immersion lens is disclosed, having a top and bottom convex surfaces. The radius of curvature of the bottom surface is larger than that of the top surface. A conical sloped side-wall connects the top and bottom surface.

Bi-convex solid immersion lens

A system for probe-less non-invasive detection of electrical signals from integrated circuit devices is disclosed. The system includes an illumination source, collection optics, imaging optics, and a photon sensor. In a navigation mode, the light source is activated and the imaging optics is used to identify the target area on the chip and appropriately position the collection optics. Once the collection optics is appropriately positioned, the light source is deactivated and the photon sensor is used to detect photons emitted from the chip. No mention of cooling (active device measurement capability) and advanced optics to detect the features (SIL).

Time resolved non-invasive diagnostics system

The fabrication of the wafer may be analyzed starting from when the wafer is in a partially fabricated state. The value of a specified performance parameter may be determined at a plurality of locations on an active area of a die of the wafer. The specified performance parameter is known to be indicative of a particular fabrication process in the fabrication. Evaluation information may then be obtained based on a variance of the value of the performance parameter of the plurality of locations. This may be done without affecting a usability of a chip that is created from the die. The evaluation information may be used to evaluate how one or more processes that include the particular fabrication process that was indicated by the performance parameter value was performed.

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San Jose, CA, United States of America

James S Vickers