Westinghouse Electric Corporation

United States of America As Represented by the Secretary of the Air Force

Northrop Corporation

James R Cricchi

Michael D Fitzpatrick

Franklyn C Blaha

Marvin H White

Joe E Brewer

David W Williams

Harry G Oehler

Gustav Cavar

David S Herman

Franklin C Blaha

Boyce T Ahlport

The process of the present invention produces CMOS bulk circuits allowing any treatment of the field oxide up to and including the channel edge; allows p-field boron implant to increase parasitic threshold eliminates the bird's beak oxide encroachment which reduces channel width and recessed oxide along the channel edge; provides for a self-aligned p-field implant; and provides for a spacer use on a self-aligned p-field implant to offset effects of side diffusion and oxide undercut. (1) Growing a field oxide layer including any specialized hardening techniques thereto on a silicon wafer; (2) Depositing a material which will serve as an implant mask such as aluminum; (3) Etching this layer to leave shapes where the thin oxide gate regions are to be; (4) Depositing a spacer material such as sputtered nitride onto the shapes; (5) Etching the spacer material; (6) Depositing a field implant mask; (7) Etching the implant mask; (8) Implanting the field regions; (9) Stripping the implant mask; (10) Stripping the spacer material if used; (11) Depositing a secondary masking layer such as Ti-W or W; (12) Bias sputtering away secondary masking material at edges of aluminum shapes; (13) Removing aluminum shapes using secondary material as a mask; (14) Etching oxide under aluminum shapes to reach the silicon wafer; (15) Stripping secondary masking layer; (16) Growing gate oxide; (17) Removing field oxide layer to expose source and drain regions in the wafer; and (18) Placing electrodes onto the drain, source, and gate regions.

Direct moat self-aligned field oxide technique

A non-volatile semiconductor memory is described incorporating a fixed threshold transistor and a variable threshold transistor in each memory cell. The fixed threshold transistor is used for row selection while the variable threshold transistor stores the data. A common memory gate line throughout the memory permits block erase to one logic state with opposite data being written in on a row-by-row basis. Information is read out from a selected row by a ramp voltage on the memory gate line which is capacitively coupled through variable threshold transistors having a channel in the body below the gate region.

Common memory gate non-volatile transistor memory

A complementary metal oxide semiconductor (CMOS) circuit is described incorporating Schottky barrier diodes in parallel with the source or drain of either the P or N channel transistors to reduce the minority current injected into the body at times the source or drain of either the N or P channel transistors are forward biased. The Schottky diode may be fabricated by making enlarged openings exposing both the body (substrate) and drain or source region and by using a metallization which may form an ohmic contact with the drain or source region and at the same time for a Schottky diode with the substrate. By incorporating Schottky barrier diodes parallel to the drain or source the P and N-type transistors are not current limited by the barrier height of only a Schottky diode acting as the source and at the same time minority current is not injected into the substrate or body at times the drain or source is forward biased. An input and output protection network is also described incorporating Schottky diodes.

Prevention of latch-up in CMOS integrated circuits using Schottky diodes

A method is described for positioning the variable threshold region of a memory transistor by a predetermined distance from the drain and source regions. The method includes providing openings in the dielectric material over the substrate at the same time or in one mask step for the variable threshold region and the drain and source regions. A mask is positioned over the variable threshold region opening at times the drain and source regions are formed. The variable threshold region is subsequently formed by growing thin oxide and a layer of nitride thereover. Both sides of the variable threshold region have a fixed threshold region between the respective drain and source which is controlled by a common gate electrode. The invention overcomes the problem of providing additional space for alignment tolerances between the variable threshold region and the drain and source regions.

Method of making self-aligned memory MNOS-transistor

A non-volatile memory has a plurality of storage bits, each bit comprising an insulated gate field effect transistor having a variable threshold voltage and selectively set to first and second stable threshold voltages in response to the application of positive and negative polarizing voltages between the gate and source thereof. The threshold voltage state of the transistor is determined by applying a read voltage having a magnitude greater than the first stable threshold voltage and less than the second stable threshold voltage, the transistor being activated only if it has assumed the first threshold voltage. Complementary addressing circuitry selectively and sequentially couples the data bits of a serial data word, received at a data terminal, to corresponding memory bits for storage in the memory. The memory bits are initially cleared by applying a positive polarizing voltage to the transistors to set them to the first stable threshold state. The addressing circuitry selectively applies a negative polarizing voltage to the transistors to set them to the second stable threshold state in accordance with the data word. The addressing circuitry also provides for interrogation of the memory by applying a read voltage to the bits in sequence and coupling the bits to the data terminal. A fire command generated by the firing of a projectile, such as an artillery shell, transfers the information in the memory to a counter. The counter is then operated at a predetermined clock rate until overflow occurs for generating a signal for detonating the explosive projectile.

Electrically resettable non-volatile memory for a fuse system

Described herein a technique for constructing a complementary MOS device on a sapphire substrate so that the surface of the device is planarized, the P-channel and N-channel devices are in substantially correct registration, the threshold voltage for the back-channel leakage effect inherent in sapphire substrate device to occur is increased, and the areas of gate oxidation are pseudo self-aligned so as to minimize overlap of the gate oxide with the source and drain regions.

High yield processing for silicon-on-sapphire CMOS integrated circuits

An MNOS non-volatile memory circuit, which inhibits the application of a write voltage to a memory cell at times when the write data is the same as the data stored in such cell to prevent saturation of the transistor, includes provision for applying automatically such a write voltage upon the detection of a predetermined weak storage condition in such cell.

Variable threshold device memory circuit having automatic refresh feature

A radiation hardened drain-source protected MNOS transistor is disclosed. A layer of silicon oxide overlies the channel and the junctions formed by the intersections of the drain and source regions with the channel. Drain and source protection is provided by relatively thick portions of the silicon oxide layer which overlie the junctions formed by the drain and source regions and the channel. The portion of the silicon oxide layer overlying the central section of the channel is thinner than the remainder of this layer. A silicon nitride layer and an electrically conductive layer forming the gate electrode overlie the thinner portion of the silicon oxide layer to complete the MNOS transistor. The conductive layer forming gate electrode of the transistor is in electrical contact with both the silicon nitride and the silicon oxide layers. This provides a convenient method for electrons generated at the interface of the silicon and the silicon-oxide layer during irradiation to be transported to the gate, thereby preventing charge build-up in the silicon oxide which causes shifts in the characteristics of the transistor.

Radiation hardened drain-source protected MNOS transistor

A complementary MOS voltage level shift circuit which can be used as a memory buffer circuit, for example, is disclosed. The circuit utilizes both N-channel depletion mode devices and P-channel enhancement mode MOS devices preferably fabricated on silicon-on-sapphire. Both types of devices are operated with only negative or zero gate-source voltage in order to minimize threshold voltage shifts in radiation environments. A capacitive voltage level shifting technique is used to obtain push-pull operation with driver type devices in order to reduce power consumption and increase switching speed while feeding into a capacitive load. Load type devices are used to prevent discharge of a capacitive load.

High speed, radiation hard complementary MOS capacitive voltage level

An MNOS memory array including circuitry to permit all of the memory devices comprising the array to be addressed for purposes of clearing the array by a block select and a clear signal as disclosed. The circuitry is arranged such that a plurality of arrays may be interconnected to form a large block oriented memory system with all blocks utilizing a common clear signal.

Circuit producing a common clear signal for erasing selected arrays in a

A processing technique utilizing two separate silicon nitride depositions (one to form the memory regions and the second to form the nonmemory regions) is employed to provide a radiation hard drain source protected memory transistor. The amount of silicon dioxide used in the nonmemory regions is also minimized. A typical device comprises a mesa etched from a silicon-on-sapphire (SOS) wafer into which P+ source and drain regions are implanted. A 100 A layer of silicon dioxide and a second 1000 A layer of nonmemory silicon nitride covers the mesa and the two layers are etched to define a substrate gate window. The gate window is covered by a 25 A layer of tunneling oxide A final 500 A layer of memory silicon nitride covers the mesa structure. Contact windows are etched to accommodate source, drain and gate interconnect electrodes.

MNOS memory transistor having a redeposited silicon nitride gate

An improved memory for storing digital data is described incorporating two variable threshold transistors per memory cell which are written in opposite directions concomitantly by applying a polarizing voltage across the gate insulator of each transistor. Subsequent writing into the memory cell is limited by means of sensing the data stored and comparing it with the data to be written to permit only write cycles where the data stored would be opposite. The variable threshold transistors are thereby operated out of saturation by shifting the voltage thresholds back and forth in opposite directions. By utilizing two variable threshold devices per memory cell, data is sensed by the difference in the conductance of the two devices providing a wider detection window.

MNOS non-volatile memory with write cycle suppression

A complementary MOS logic circuit is disclosed. The circuit utilizes two stages with a coupling network comprising a capacitor and a diode used to couple the first stage to the second stage. This results in a circuit with the logic signal coupled to the input being inverted at the output without introducing substantial loss in signal amplitude.

Complementary MOS logic circuit

An improved drain source protected MNOS transistor is realized by means of a fabrication technique that permits independent control of memory and nonmemory parameters. Self alignment of memory regions during fabrication is achieved by using nitride masking for gate oxidation. Independent control of memory and nonmemory parameters derives from a device configuration in which protected regions consist exclusively of gate oxide and silicon nitride is present only in the memory regions. Transistor radiation hardening is also achieved by elimination of the nitride layer above the device's thin silicon dioxide regions.

Drain source protected MNOS transistor and method of manufacture

An MOS transistor constructed using silicon on sapphire technology in which the channel region can be electrically connected either to the source or drain terminal is disclosed. The transistor is advantageous in that the shift of the threshold voltage of the transistor in the presence of radiation is substantially decreased. Connecting the channel region of the transistor to the source terminal also substantially reduces what is normally referred to as the 'kink' effect in MOS transistors utilizing floating substrate channel regions. Reducing the sensitivity to radiation and the kink effect results in a transistor having improved electrical characteristics.

Growing community of inventors

Catonsville, MD, United States of America

James R Cricchi