Synopsys, Inc.

James Patrick Shiely

Hua Song

Lawrence S Melvin, Iii

Qiliang Yan

Benjamin David Painter

Gerard Luk-Pat

Cheng En Wu

Yuelin Du

Zhijie Deng

Jianliang Li

Qiaolin Zhang

Alexander Miloslavsky

Lena Zavyalova

Irene Y Su

Lantian Wang

Systems and techniques for three-dimension (3D) resist profile aware resolution enhancement techniques are described. 3D resist profile aware resolution enhancement models can be calibrated based on empirical data. Next, the 3D resist profile aware resolution enhancement models can be used in one or more applications, including, but not limited to, lithography verification, etch correction, optical proximity correction, and assist feature placement.

3D resist profile aware resolution enhancement techniques

Systems and techniques for using a three-dimension (3D) resist profile aware etch-bias model are described. A 3D resist profile aware etch-bias model can be calibrated based on empirical data. Next, the 3D resist profile aware etch-bias model can be used in one or more applications, including, but not limited to, lithography verification, etch correction, optical proximity correction, and assist feature placement.

3D resist profile aware etch-bias model

Processes and apparatuses are described for modeling and correcting electron-beam (e-beam) proximity effects during e-beam lithography. An uncalibrated e-beam model, which includes a long-range component and a short-range component, can be calibrated based on one or more test layouts. During correction, a first resist intensity map can be computed based on the long-range component of the calibrated e-beam model and a mask layout. Next, a target pattern in the mask layout can be corrected by, iteratively: (1) computing a second resist intensity map based on the short-range component of the calibrated e-beam model and the target pattern; (2) obtaining a combined resist intensity map by combining the first resist intensity map and the second resist intensity map; and (3) adjusting the target pattern based on the combined resist intensity map and the design intent.

Modeling and correcting short-range and long-range effects in E-beam lithography

Computer-readable medium and methods for photolithographic simulation of scattering. A design layout comprising a layout polygon is received. A skeleton representation of a mask shape that is created responsive to e-beam writing of the layout polygon is generated. The skeleton representation is defined by a plurality of skeleton points. Individual scattering patterns for the skeleton points are selected from a lookup table of pre-determined scattering patterns. Each of the individual scattering patterns representing an amount of optical scattering for a corresponding one of the skeleton points. A simulated wafer image is produced responsive to the individual scattering patterns.

Fast 3D mask model based on implicit countors

Mask design techniques for detection and removal of undesirable artifacts in SADP processes using multiple patterns are disclosed. Artifacts or spurs result from lithographic and chemical processing of semiconducting wafers. The spurs are undesirable because they can cause unwanted connections or act as electrical antennas. Spurs are detected using rule-based techniques and reduced by modifying lithographic masks. The severity of the detected spurs is determined, again using rule-based techniques. The effects of detected spurs can be reduced by modifying the decomposition of the drawn patterns into the two masks used for lithography. Mandrel masks are modified by add dummy mandrel material, and trim masks are modified by removing trim material. The resulting multi-pattern arrangement is used to fabricate the critical design elements that make up the semiconductor wafers.

Detection and removal of self-aligned double patterning artifacts

Mask design techniques for sharp corner printing in liquid crystal displays are disclosed using multiple patterns. The viewing angle and color quality of thin film transistor liquid crystal displays are largely dependent upon electrode corner sharpness as patterned in a given metal layer. Depending on design style, critical elements include convex angles, concave angles, or both convex and concave angles. Angle sharpness is dependent upon the resolution limit of a given exposure system. Since critical design element requirements exceed the capabilities of one mask, two or more masks are implemented. The determination of critical pattern features within a given layer identifies angles that are problematic for fabrication. The critical pattern features are decomposed into multiple mask layers. The resulting multi-pattern arrangement is used to fabricate the critical design elements that make up the needed angles.

Multi-patterning for sharp corner printing

Systems and techniques for modeling the EUV lithography shadowing effect are described. Some embodiments described herein provide a process model that includes an EUV lithography shadowing effect component. Polygon edges in a layout can be dissected into a set of segments. Next, the EUV lithography shadowing effect component can be used to bias each segment. The modified layout having the biased segments can then be used as input for other components in the process model.

Modeling EUV lithography shadowing effect

Extreme ultraviolet (EUV) lithography flare calculation and compensation is disclosed herein. A method of calculating flare for a mask for use in EUV lithography includes decomposing the flare power spectrum density (PSD) into a low frequency component and a high frequency component. Further, the method includes receiving a plurality of layouts in a flare map generator. Each of the plurality of layouts corresponds to a chip pattern location on the mask. Moreover, the method includes generating, using the flare map generator, a low frequency flare map for the mask from the low frequency component by using fast Fourier transform (FFT).

EUV lithography flare calculation and compensation

One embodiment of the present invention provides a system that determines image intensity at a location in a photoresist (PR) layer on a wafer. During operation, the system receives a set of masks which were used to generate one or more patterned layers of a multilayer structure on the wafer, wherein a patterned layer includes a set of reflectors on a top surface of the patterned layer, which correspond to patterns in a patterned-layer mask in the set of masks, wherein a reflector reflects light from a light source during a photolithography process. The system then generates a first virtual mask based on the first mask and the patterned-layer mask, wherein the first virtual mask uses a clear area to model a reflector in the set of reflectors. Next, the system determines the image intensity value at the location on the PR layer based at least on the first mask and the first virtual mask.

Modeling thin-film stack topography effect on a photolithography process

A system includes a conversion module that preserves the shape of a contour when converting an image to a different resolution. The conversion module receives a first image and divides the first image into regions of pixel values. For each region, a contribution of the region to the pixel values in the second image is determined. The contribution is selected from a set of pre-determined contributions that are a nonlinear function of the values in the region, and the selection is made based at least in part on the values in the region. The contributions are accumulated together to generate a second image. The conversion module may be, for example, part of a design flow for an integrated circuit that connects a mask simulation stage with an optical simulation stage.

Non-linear rasterized contour filters

One embodiment of the present invention provides a system that performs lithography verification for a double-patterning process on a mask layout without performing a full contour simulation of the mask layout. During operation, the system starts by receiving a first mask which is used in a first lithography step of the double-patterning process, and a second mask which is used in a second lithography step of the double-patterning process. Note that the first mask and the second mask are obtained by partitioning the mask layout. Next, the system receives an evaluation point on the mask layout. The system then determines whether the evaluation point is exclusively located on a polygon of the first mask, exclusively located on a polygon of the second mask, or located elsewhere. The system next computes a printing indicator at the evaluation point for the mask layout based on whether the evaluation point is exclusively located on a polygon of the first mask or exclusively located on a polygon of the second mask.

Method and system for performing lithography verification for a double-patterning process

One embodiment of the present invention provides a system that reduces computational complexity in simulating an image resulting from an original mask and an optical transmission system. During operation, the system obtains a set transmission cross coefficient (TCC) kernel functions based on the optical transmission system, and obtains a set of transmission functions for a representative pattern which contains features representative of the original mask. The system constructs a new set of kernel functions based on the TCC kernel functions and the transmission functions for the representative pattern, wherein responses to the new kernel functions in a resulting image corresponding to the representative pattern are substantially uncorrelated with one another. The system further produces an intensity distribution of a resulting image corresponding to the original mask based on the new kernel functions, thereby facilitating prediction of a layout that can be produced from the original mask.

Method and system for correlating physical model representation to pattern layout

One embodiment of the present invention provides a system that identifies an area in a mask layout which is likely to cause manufacturing problems. During operation, the system creates an on-target process model that models a semiconductor manufacturing process under nominal (e.g., optimal) process conditions. The system also creates one or more off-target process models that model the semiconductor manufacturing process under one or more arbitrary (e.g., non-optimal) process conditions. Next, the system computes a process-sensitivity model using the on-target process model and the off-target process models. The system then computes a gradient-magnitude of the process-sensitivity model. Next, the system identifies a problem area in the mask layout using the gradient-magnitude of the process-sensitivity model. Note that identifying the problem area allows it to be corrected, which improves the manufacturability of the mask layout. Moreover, using the gradient-magnitude of the process-sensitivity model to identify the problem area reduces the computational time required to identify the problem area.

Method and apparatus for identifying a manufacturing problem area in a layout using a gradient-magnitude of a process-sensitivity model

One embodiment of the present invention provides a system that improves the depth of focus during an optical lithography process. During operation, the system receives a mask layout. The system then selects an edge in the mask layout. Next, the system adds a notch to the edge to improve the depth of focus by helping to maintain a critical dimension associated with the edge as the optical lithography process drifts out of focus. Note that adding a notch to the edge adds a high spatial-frequency component to the mask layout. This high spatial-frequency component degrades as the optical lithography process drifts out of focus. This degradation causes the mask layout to allow more light into the pattern, which helps maintain the critical dimension, thereby improving depth of focus.

Method and apparatus for improving depth of focus during optical lithography

One embodiment of the present invention provides a system that identifies a problem edge in a mask layout which is likely to have manufacturing problems. During operation, the system creates an on-target process model that models a semiconductor manufacturing process under nominal process conditions. The system also creates one or more off-target process models that model the semiconductor manufacturing process under one or more process conditions that are different from nominal process conditions. Next, the system computes a process-sensitivity model using the on-target process model and the off-target process models. The system then computes an edge-detecting process-sensitivity model by convolving the process-sensitivity model with an edge-detecting function which can be used to detect edges in an image. Next, the system identifies a problem edge in the mask layout using the edge-detecting process-sensitivity model.

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Aloha, OR, United States of America

James Patrick Shiely