Lsi Logic Corporation

Lsi Corporation

James O Kimball

Sheldon Aronowitz

Douglas Ticknor Grider

Gobi R Padmanabhan

David C Lee

Valeriy K Sukharev

John Haywood

Yu-Lam Ho

Chi-Yi Kao

David Chan

Laique Khan

Techniques for vaporizing and handling a vaporized metallic element or metallic element salt with a heated inert carrier gas for further processing. The vaporized metallic element or salt is carried by an inert carrier gas heated to the same temperature as the vaporizing temperature to a heated processing chamber. The metal or salt vapor may be ionized (and implanted) or deposited on substrates. Apparatus for accomplishing these techniques, which include carrier gas heating chambers and heated processing chambers are also provided.

Method of treating metal and metal salts to enable thin layer deposition in semiconductor processing

Method of vaporizing and ionizing metals for use in semiconductor processing

Vaporization and ionization of metals for use in semiconductor processing

Lifetime of a short-channel NMOS device is increased by modifying distributions of electrically active LDD dopant at boundaries of the device's LDD regions. The LDD dopant distributions are modified by implanting counter-dopants at the boundaries of the LDD regions. Group III counter-dopants such as boron and group IV elements such as silicon alter activation properties of the LDD dopant. The dopant distributions are modified at the device's n-junctions to reduce the maximum electric field displacement at an interface defined by the device's gate and substrate. The dopant distributions can be further modified to shape the n-junctions such that hot carriers are injected away from the gate.

FETs having lightly doped drain regions that are shaped with counter and noncounter dorant elements

Provided are methods for fabricating hardened composite thin layer gate dielectrics. According to preferred embodiments of the present invention, composite gate dielectrics may be produced as bilayers having oyxnitride portions with nitrogen contents above 10 atomic percent, while avoiding the drawbacks of prior art nitridization methods. In one aspect of the present invention, a hardened composite thin layer gate dielectric may be formed by deposition of a very thin silicon layer on a very thin oxide layer on a silicon substrate, followed by low energy plasma nitridization and subsequent oxidation of the thin silicon layer. In another aspect of the invention, low energy plasma nitridization of a thin oxide layer formed on a silicon substrate may be followed by deposition of a very thin silicon layer and subsequent oxidation, or additional low energy plasma nitridization and then oxidation, of the thin silicon layer.

Composite semiconductor gate dielectrics

Provided is a method of fabricating gate dielectric layers having variable thicknesses and compositions over different regions of a semiconductor wafer. In a preferred embodiment of the present invention, a gate oxide layer is first grown over the various regions. Regions that are to have a relatively thicker, unhardened gate dielectric are masked and the wafer is exposed to a remote low energy nitrogen plasma. After the nitridization process is completed, the mask is removed and the wafer is exposed to further oxidation. The regions where oxynitrides have been formed act as a barrier to the oxidation process. Consequently, different oxide thicknesses can be grown on the same wafer, thinner and hardened where nitridization has been performed, and thicker and not hardened in those regions that were masked during the nitridization. Variable thickness gate dielectrics in accordance with the present invention may be particularly advantageous in semiconductor integrated circuits involving both digital and analog devices.

Method of forming variable thickness gate dielectrics

A retrograde well in a CMOS device is formed by using a low energy ion implanter. Dopant atoms are implanted into a bare surface of the device's substrate, in a direction that is orthogonal to the surface of the substrate (for a substrate having a &lt;100&gt; orientation). The well implant can be performed at an energy below 220 keV. Chained implants for a punch-through barrier in the retrograde well can be performed after the well implant. When the substrate is annealed, the punch-through barrier is activated at the same time as the retrograde well.

Method of forming retrograde well structures and punch-through barriers

A process is disclosed for forming one or more doped regions beneath the surface of a single crystal semiconductor substrate, such as retrograde wells or deeper source/drain regions, by implantation at low energy which comprises orienting the crystal lattice of the semiconductor substrate, with respect to the axis of the implantation beam, i.e., the path of the energized atoms in the implantation beam, to maximize the number of implanted atoms which pass between the atoms in the crystal lattice. This results in the peak concentration of implanted atoms in the crystal lattice of the single crystal semiconductor substrate being deeper than the peak concentration of implanted atoms in the substrate would be if the axis of the implantation beam were not so oriented with respect to the crystal lattice of the semiconductor substrate during implantation.

Process for low energy implantation of semiconductor substrate using

Formation of a barrier region in a single crystal group IV semiconductor substrate at a predetermined spacing from a doped region in the substrate is described to prevent or inhibit migration of dopant materials from an adjacent doped region through the barrier region. By implantation of group IV materials into a semiconductor substrate to a predetermined depth in excess of the depth of a doped region, a barrier region can be created in the semiconductor to prevent migration of the dopants from the doped region through the barrier region. The treatment of the single crystal substrate with the group IV material is carried out at a dosage and energy level sufficient to provide such a barrier region in the semiconductor substrate, but insufficient to result in amorphization (destruction) of the single crystal lattice of the semiconductor substrate.

Process for making group IV semiconductor substrate treated with one or

A process and resulting product is described for forming an oxide in a semiconductor substrate which comprises initially implanting the substrate with atoms of a noble gas, then oxidizing the implanted substrate at a reduced temperature, e.g., less than 900.degree. C., to form oxide in the implanted region of the substrate, and then etching the oxidized substrate to remove a portion of the oxide. The resulting oxidation produces a dual layer of oxide in the substrate. The upper layer is an extremely porous and frothy layer of oxide, while the lower layer is a more dense oxide. The upper porous layer of oxide can be selectively removed from the substrate by a mild etch, leaving the more dense oxide layer in the substrate. Further oxide can then be formed adjacent the dense layer of oxide in the substrate, either by oxide deposition over the dense oxide or by growing further oxide beneath the dense oxide layer. The initial oxide formed by the process appears to be temperature independent, at temperatures of 900.degree. C. or less, with oxide formation apparently dependent upon the extent of the implanted regions of the substrate, rather than upon temperature, resulting in thermal savings. Furthermore, the excess implanted noble gas in the substrate adjacent the oxide formed therein can have beneficial effects in inhibiting the formation of parasitic field transistors and in greater control over field thresholds.

Oxide formed in semiconductor substrate by implantation of substrate

A process and resulting product are described for controlling the channeling and/or diffusion of a boron dopant in a P- region forming the lightly doped drain (LDD) region of a PMOS device in a single crystal semiconductor substrate, such as a silicon substrate. The channeling and/or diffusion of the boron dopant is controlled by implanting the region, prior to implantation with a boron dopant, with noble gas ions, such as argon ions, at a dosage at least equal to the subsequent dosage of the implanted boron dopant, but not exceeding an amount equivalent to the implantation of about 3.times.10.sup.14 argon ions/cm.sup.2 into a silicon substrate, whereby channeling and diffusion of the subsequently implanted boron dopant is inhibited without, however, amorphizing the semiconductor substrate.

Substrate with controlled amount of noble gas ions to reduce channeling

Formation of a barrier region in a single crystal group IV semiconductor substrate at a predetermined spacing from a doped region in the substrate is described to prevent or inhibit migration of dopant materials from an adjacent doped region through the barrier region. By implantation of group IV materials into a semiconductor substrate to a predetermined depth in excess of the depth of a doped region, a barrier region can be created in the semiconductor to prevent migration of the dopants from the doped region through the barrier region. The treatment of the single crystal substrate with the group IV material is carried out at a dosage and energy level sufficient to provide such a barrier region in the semiconductor substrate, but insufficient to result in amorphization (destruction) of the single crystal lattice of the semiconductor substrate. In another embodiment, a similar barrier region may be formed in the semiconductor substrate but at a depth less than that of the doped region to inhibit migration of the dopant to the surface of the substrate. Such barrier regions may be formed in the substrate both above and below the doped region to inhibit migration of the dopant in the doped region in either direction.

A process and resulting product are described for controlling the channeling and/or diffusion of a boron dopant in a P- region forming the lightly doped drain (LDD) region of a PMOS device in a single crystal semiconductor substrate, such as a silicon substrate. The channeling and/or diffusion of the boron dopant is controlled by implanting the region, prior to implantation with a boron dopant,, with noble gas ions, such as argon ions, at a dosage at least equal to the subsequent dosage of the implanted boron dopant, but not exceeding an amount equivalent to the implantation of about 3.times.10.sup.13 argon ions/cm.sup.2 into a silicon substrate, whereby channeling and diffusion of the subsequently implanted boron dopant is inhibited without, however, amorphizing the semiconductor substrate.

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San Jose, CA, United States of America

James O Kimball