Advanced Micro Devices Corporation

Fairchild Semiconductor Corporation

Other

International Business Machines Corporation

Globalfoundries Inc.

Advanced Micro Device, Inc.

James N Pan

Qi Xiang

Jung-Suk Goo

Paul Raymond Besser

Minh Van Ngo

John G Pellerin

Jinsong Yin

Christy Mei-Chu Woo

Qi Wang

Christy M-c Woo

Ming-Ren Lin

Jon D Cheek

Witold P Maszara

Allen S Yu

James J Murphy

Andrew Michael Waite

Ming Lin

Ihsan Djomehri

Bruce Bennett Doris

Takashi Ando

Hamza Yilmaz

Vijay Narayanan

Michael Patrick Chudzik

Matthew S Buynoski

Eduard Albert Cartier

Vamsi Krishna Paruchuri

Rajarao Jammy

Eric N Paton

Dean E Probst

Joseph Andrew Yedinak

Srinath Krishnan

Sey-Ping Sun

Rodney S Ridley

Young-Hee Kim

Linda R Black

Praveen Muraleedharan Shenoy

Changhwan Choi

Christopher Lawrence Rexer

Mark L Rinehimer

Jonathan B Smith

Jaegil Lee

Dwayne S Reichl

Hui Chen

Hossein Paravi

Scott L Hunt

Rodney S Ridley, Sr

Briant Harward

Elizabeth A Duch

Harold Heidenreich

Chongman Yun

Josph A Yedinak

Christopher L Rexer

In one embodiment, an apparatus can include a trench extending into a semiconductor region of a first conductivity type, an electrode disposed in the trench, and a source region of the first conductivity type abutting a sidewall of the trench. The apparatus can include a first well region of a second conductivity type disposed in the semiconductor region below the source region and abutting the sidewall of the trench lateral to the electrode where the second conductivity type is opposite the first conductivity type. The apparatus can also include a second well region of the second conductivity type disposed in the semiconductor region and abutting the sidewall of the trench, and a third well region of the first conductivity type disposed between the first well region and the second well region.

Shielded gate trench FET with multiple channels

A method for forming a semiconductor structure includes the following steps. Trenches are formed in a semiconductor region using a masking layer such that the trenches have a first depth, a first width along their bottom, and sidewalls having a first slope. The masking layer is removed, and a bevel etch is performed to taper the sidewalls of the trenches so that the sidewalls have a second slope less than the first slope.

Technique for controlling trench profile in semiconductor structures

A power device includes a semiconductor substrate having a plurality of alternately arranged pillars of first and second conductivity types. At least one of the plurality of pillars of second conductivity type includes a first trench epitaxial layer of the second conductivity type disposed on a trench sidewall of the second trench and a trench bottom surface of the second trench, a second trench epitaxial layer of the second conductivity type disposed on the first trench epitaxial layer of the second conductivity type, and an insulating material layer disposed on the second trench epitaxial layer of the second conductivity type.

Superjunction structures for power devices and methods of manufacture

A method of fabricating a semiconductor device having a transistor with a metal gate electrode and a gate dielectric layer includes forming a protective layer on the gate dielectric layer and forming a metal gate electrode over the protective layer. The protective layer has a graded composition between the gate dielectric layer and the metal gate electrode.

Replacement metal gate transistors with reduced gate oxide leakage

A semiconductor structure which includes a shielded gate FET is formed as follows. A plurality of trenches is formed in a semiconductor region using a mask. The mask includes (i) a first insulating layer over a surface of the semiconductor region, (ii) a first oxidation barrier layer over the first insulating layer, and (iii) a second insulating layer over the first oxidation barrier layer. A shield dielectric is formed extending along at least lower sidewalls of each trench. A thick bottom dielectric (TBD) is formed along the bottom of each trench. The first oxidation barrier layer prevents formation of a dielectric layer along the surface of the semiconductor region during formation of the TBD. A shield electrode is formed in a bottom portion of each trench. A gate electrode is formed over the shield electrode in each trench.

Structure related to a thick bottom dielectric (TBD) for trench-gate devices

A semiconductor device includes a semiconductor-on-insulator region on a substrate. The semiconductor-on-insulator region includes a first semiconductor region overlying a dielectric region. The device includes an MOS transistor and a bipolar transistor. The MOS transistor has a drain region, a body region, and a source region in the first semiconductor region. The MOS transistor also includes a gate. The device also includes a second semiconductor region overlying the substrate and adjacent to the drain region, and a third semiconductor region overlying the substrate and adjacent to the second semiconductor region. The bipolar transistor includes has the drain region of the MOS transistor as an emitter, the second semiconductor region as a base, and the third semiconductor region as a collector. Accordingly, the drain of the MOS transistor also functions as the emitter of the bipolar transistor. Additionally, the gate and the base are coupled by a resistive element.

Structure and method for semiconductor power devices

A semiconductor device has a substrate, a gate dielectric layer, and a metal gate electrode on the gate dielectric layer. The gate dielectric layer includes an oxide layer having a dielectric constant (k) greater than 4, and silicon concentrated at interfaces of the oxide layer with the substrate and with the metal gate electrode. A method of fabricating a semiconductor device includes forming a removable gate over a substrate with a gate dielectric layer between the removable gate and the substrate, forming a dielectric layer over the substrate and exposing an upper surface of the removable gate, removing the removable gate leaving an opening in the dielectric layer, forming a protective layer on the gate dielectric layer and lining the opening, and forming a metal gate electrode in the opening. The protective layer has a graded composition between the gate dielectric layer and the metal gate electrode.

A method for forming a shielded gate trench field effect transistor (FET) includes forming trenches in a semiconductor region, forming a shield electrode in a bottom portion of each trench, and forming an inter-electrode dielectric (IED) extending over the shield electrode. The IED may comprise a low-k dielectric. The method also includes forming a gate electrode in an upper portion of each trench over the IED.

Shielded gate trench FET with an inter-electrode dielectric having a low-k dielectric therein

A semiconductor structure comprises trenches extending into a semiconductor region. Portions of the semiconductor region extend between adjacent trenches forming mesa regions. A gate electrode is in each trench. Well regions of a first conductivity type extend in the semiconductor region between adjacent trenches. Source regions of a second conductivity type are in the well regions. Heavy body regions of the first conductivity type are in the well regions. The source regions and the heavy body regions are adjacent trench sidewalls, and the heavy body regions extend over the source regions along the trench sidewalls to a top surface of the mesa regions.

High density trench field effect transistor

A vertically-conducting planar-gate field effect transistor includes a silicon region of a first conductivity type, a silicon-germanium layer extending over the silicon region, a gate electrode laterally extending over but being insulated from the silicon-germanium layer, a body region of the second conductivity type extending in the silicon-germanium layer and the silicon region, and source region of the first conductivity type extending in the silicon-germanium layer. The gate electrode laterally overlaps both the source and body regions such that a portion of the silicon germanium layer extending directly under the gate electrode between the source region and an outer boundary of the body region forms a channel region.

Structure and method for forming planar gate field effect transistor with low resistance channel region

A semiconductor structure comprises a drift region of a first conductivity type in a semiconductor region. A well region of a second conductivity type is over the drift region. A source region of the first conductivity type is in an upper portion of the well region. A heavy body region of the second conductivity type extends in the well region. The heavy body region has a higher doping concentration than the well region. A first diffusion barrier region at least partially surrounds the heavy body region. A gate electrode is insulated from the semiconductor region by a gate dielectric.

Structures for reducing dopant out-diffusion from implant regions in power devices

A strain enhanced semiconductor device and methods for its fabrication are provided. One method comprises embedding a strain inducing semiconductor material in the source and drain regions of the device to induce a strain in the device channel. Thin metal silicide contacts are formed to the source and drain regions so as not to relieve the induced strain. A layer of conductive material is selectively deposited in contact with the thin metal silicide contacts, and metallized contacts are formed to the conductive material.

Strain enhanced semiconductor devices and methods for their fabrication

In one embodiment, the invention is a method and apparatus for fabricating a high-performance band-edge complementary metal-oxide-semiconductor device. One embodiment of a method for fabricating a complementary metal-oxide-semiconductor device includes fabricating an n-type metal-oxide-semiconductor device using a gate first process, and fabricating a p-type metal-oxide-semiconductor device using a gate last process.

Method and apparatus for fabricating a high-performance band-edge complementary metal-oxide-semiconductor device

The CMOS field effect transistors, used in microprocessors and other digital VLSI circuits, face major challenges such as thin gate dielectrics leakage and scaling limits, severe short channel effects, limited performance improvement with scaling, complicated fabrication process with added special techniques, and surface mobility degradation. This disclosure proposes a new CMOS-compatible optoelectronic transistor. The current is much higher than the MOS transistors, due to the high carrier mobility with bulk transportation. The optoelectronic transistors are scalable to the sub-nanometer ranges without short channel effects. It is also suitable for low power applications and ULSI circuits. The new transistor consists of a laser or LED diode as drain or source, and a photo sensor diode (avalanche photo diode) as source or drain. The transistor is turned on by applying a gate voltage, similar to the CMOS transistors, and a laser or LED light signal is sent to the nearby photo diode, causing an avalanche breakdown and high drain current. The transistor is surrounded by dielectrics and metal isolations, which serve as a metal box or cavity, so the generated laser or LED lights are confined and reflected back from the metal. The drain current increases exponentially with the drain or gate voltage. This exponential drain current vs. drain or gate voltage characteristics makes the optoelectronic transistor run much faster than the transitional linear MOSFET. The optic transistor current-voltage characteristics are totally different from transitional CMOS transistors.

Resonant cavity complementary optoelectronic transistors

Thin effective gate oxide thickness with reduced leakage for replacement metal gate transistors is achieved by forming a protective layer between the gate oxide layer and metal gate electrode, thereby reducing stress. Embodiments include forming a protective layer of amorphous carbon containing metal carbides decreasing in concentration from the metal gate electrode toward the gate oxide layer across the protective layer. Embodiments of methodology include removing the removable gate, depositing a layer of amorphous carbon on the gate oxide layer, forming the metal gate electrode and then heating at an elevated temperature to diffuse metal from the metal gate electrode into the amorphous carbon layer, thereby forming the metal carbides. Embodiments also include metal gate transistors with a gate oxide layer having a high dielectric constant and silicon concentrated at the interfaces with the metal gate electrode and substrate.

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Fishkill, NY, United States of America

James N Pan