Intel Corporation

Massachusetts Institute of Technology

James M Blackwell

Robert L Bristol

Marie Krysak

Florian Gstrein

Kevin Lai Lin

Rami Hourani

Eungnak Han

Manish Chandhok

Matthew V Metz

Jeffery D Bielefeld

Willy Rachmady

David J Michalak

Richard E Schenker

Scott Bruce Clendenning

Tayseer Mahdi

Lauren Doyle

Jack T Kavalieros

Suman Datta

James S Clarke

Charles Henry Wallace

Swaminathan Sivakumar

Paul Anton Nyhus

Elliot Tan

Patricio E Romero

Curtis W Ward

Robert S Chau

Mark L Doczy

Justin K Brask

Noriyuki Sato

Elijah V Karpov

Hui Jae Yoo

Christopher J Jezewski

Ramanan Chebiam

Carl H Naylor

Miriam Ruth Reshotko

Tristan A Tronic

Nafees Kabir

Michael Christenson

Jiun-Ruey Chen

Shane M Harlson

Alan M Myers

Grant M Kloster

John J Plombon

Kanwal Jit Singh

Gopinath Bhimarasetti

Gurpreet Singh

Jessica M Torres

Patrick Theofanis

Kent N Frasure

Marko Radosavljevic

Brian S Doyle

Uday Shah

Amlan Majumdar

Jeanette M Roberts

Mantu K Hudait

Harsono S Simka

Darryl Morrison

Daniel B Bergstrom

Paul A Zimmerman

Christopher Colin Cummins

Todd R Younkin

Michael Robinson

Brandon Jay Holybee

Xuanxuan Chen

Cen Tan

Emily Walker

Brian Zaccheo

Gregory J Kearns

IC interconnect structures including subtractively patterned features. Feature ends may be defined through multiple patterning of multiple cap materials for reduced misregistration. Subtractively patterned features may be lines integrated with damascene vias or with subtractively patterned vias, or may be vias integrated with damascene lines or with subtractively patterned lines. Subtractively patterned vias may be deposited as part of a planar metal layer and defined currently with interconnect lines. Subtractively patterned features may be integrated with air gap isolation structures. Subtractively patterned features may be include a barrier material on the bottom, top, or sidewall. A bottom barrier of a subtractively patterned features may be deposited with an area selective technique to be absent from an underlying interconnect feature. A barrier of a subtractively patterned feature may comprise graphene or a chalcogenide of a metal in the feature or in a seed layer.

Subtractively patterned interconnect structures for integrated circuits

Bottom-up fill dielectric materials for semiconductor structure fabrication, and methods of fabricating bottom-up fill dielectric materials for semiconductor structure fabrication, are described. In an example, a method of fabricating a dielectric material for semiconductor structure fabrication includes forming a trench in a material layer above a substrate. A blocking layer is formed partially into the trench along upper portions of sidewalls of the trench. A dielectric layer is formed filling a bottom portion of the trench with a dielectric material up to the blocking layer. The blocking layer is removed. The forming the blocking layer, the forming the dielectric layer, and the removing the blocking layer are repeated until the trench is completely filled with the dielectric material.

Bottom-up fill dielectric materials for semiconductor structure fabrication and their methods of fabrication

Disclosed herein are diamondoid materials in quantum computing devices, as well as related methods, devices, and materials. For example, in some embodiments, a quantum computing device may include: qubit circuitry, an interconnect in conductive contact with the qubit circuitry, and a dielectric material proximate to the interconnect, wherein the dielectric material includes a diamondoid film.

Diamondoid materials in quantum computing devices

Advanced lithography techniques including sub-10 nm pitch patterning and structures resulting therefrom are described. Self-assembled devices and their methods of fabrication are described.

Advanced lithography and self-assembled devices

A chemical composition includes a polymer chain having a surface anchoring group at a terminus of the polymer chain. The surface anchoring group is metal or dielectric selective and the polymer chain further includes at least one of a photo-acid generator, quencher, or a catalyst. In some embodiments, the surface anchoring group is metal selective or dielectric selective. In some embodiments, the polymer chain includes side polymer chains where the side polymer chains include polymers of photo-acid generators, quencher, or catalyst.

Chemical compositions and methods of patterning microelectronic device structures

Embodiments herein describe techniques for a semiconductor device including an interconnect structure. The interconnect structure may have a segment of a passivant layer including a SAM. The SAM may include head groups, and chains attached to the head groups. The chains include functional groups that are cross-linkable at end or side of the chains to result in chain extension by reacting with another SAM or polymer, densification by crosslinking with an adjacent SAM, or polymerization having an initiator as the SAM or the SAM attached to another SAM. Other embodiments may be described and/or claimed.

Interconnect structure surface modifications by passivating agents

Disclosed herein are structures and techniques utilizing directed self-assembly for microelectronic device fabrication. For example, a microelectronic structure may include a patterned region including a first conductive line and a second conductive line, wherein the second conductive line is adjacent to the first conductive line; and an unordered region having an unordered lamellar pattern, wherein the unordered region is coplanar with the patterned region.

Directed self-assembly structures and techniques

Techniques, structures, and materials related to extreme ultraviolet (EUV) lithography are discussed. Multiple patterning inclusive of first patterning a grating of parallel lines and second patterning utilizing EUV lithography to form plugs in the grating, and optional trimming of the plugs may be employed. EUV resists, surface treatments, resist additives, and optional processing inclusive of plug healing, angled etch processing, electric field enhanced post exposure bake are described, which provide improved processing reliability, feature definition, and critical dimensions.

EUV patterning methods, structures, and materials

Approaches based on differential hardmasks for modulation of electrobucket sensitivity for semiconductor structure fabrication, and the resulting structures, are described. In an example, a method of fabricating an interconnect structure for an integrated circuit includes forming a hardmask layer above an inter-layer dielectric (ILD) layer formed above a substrate. A plurality of dielectric spacers is formed on the hardmask layer. The hardmask layer is patterned to form a plurality of first hardmask portions. A plurality of second hardmask portions is formed alternating with the first hardmask portions. A plurality of electrobuckets is formed on the alternating first and second hardmask portions and in openings between the plurality of dielectric spacers. Select ones of the plurality of electrobuckets are exposed to a lithographic exposure and removed to define a set of via locations.

Differential hardmasks for modulation of electrobucket sensitivity

Lined photoresist structures to facilitate fabricating back end of line (BEOL) interconnects are described. In an embodiment, a hard mask has recesses formed therein, wherein liner structures are variously disposed each on a sidewall of a respective recess. Photobuckets comprising photoresist material are also variously disposed in the recesses. The liner structures variously serve as marginal buffers to mitigate possible effects of misalignment in the exposure of photoresist material to photons or an electron beam. In another embodiment, a recess has disposed therein a liner structure and a photobucket that are both formed by self-assembly of a photoresist-based block-copolymer.

Lined photobucket structure for back end of line (BEOL) interconnect formation

Two-stage bake photoresists with releasable quenchers for fabricating back end of line (BEOL) interconnects are described. In an example, a photolyzable composition includes an acid-deprotectable photoresist material having substantial transparency at a wavelength, a photo-acid-generating (PAG) component having substantial transparency at the wavelength, and a base-generating component having substantial absorptivity at the wavelength.

Two-stage bake photoresist with releasable quencher

A photosensitive composition including metal nanoparticles capped with an organic ligand, wherein the metal particles includes a metal that absorbs light in the extreme ultraviolet spectrum. A method including synthesizing metal particles including a diameter of 5 nanometers or less, wherein the metal particles includes a metal that absorbs light in the extreme ultraviolet spectrum; and capping the metal particles with an organic ligand. A method including depositing a photosensitive composition on a semiconductor substrate, wherein the photosensitive composition includes metal nanoparticles capped with an organic ligand and the nanoparticles include a metal that absorbs light in the extreme ultraviolet spectrum; exposing the photosensitive composition to light in an ultraviolet spectrum through a mask including a pattern; and transferring the mask pattern to the photosensitive composition.

Ligand-capped main group nanoparticles as high absorption extreme ultraviolet lithography resists

A photoresist is disclosed. The photoresist includes a polymer with one repeating unit and an absorbing unit.

Chain scission photoresists and methods for forming chain scission photoresists

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Portland, OR, United States of America

James M Blackwell