Texas Instruments Corporation

James L Oborny

Margaret Simmons-Matthews

Daniel Joseph Stillman

William John Antheunisse

Norman Armendariz

Ramyanshu Datta

Kenneth Michael Butler

Thiha Shwe

Hisashi Ata

Jeff A West

John Allen Hite

An interposer comprises an insulating substrate having a first side and a second side; a first plurality of metal contacts on the first side; a second plurality of metal contacts on the second side; and a plurality of cuts through the insulating substrate. The plurality of cuts comprise a first cut between a first metal contact in the first plurality of metal contacts and a second metal contact in the first plurality of metal contacts, and between a first metal contact in the second plurality of metal contacts and a second metal contact in the second plurality of metal contacts.

Interposers having cuts through an insulating substrate

A method of topside only dual-side testing of an electronic assembly includes providing a singulated through substrate via (TSV) die flip chip attached to a die support including a package substrate. The TSVs on the TSV die extend from its frontside to contactable TSV tips on its bottomside. The TSVs on the frontside of the TSV die are coupled to embedded topside substrate pads on a top surface of the ML substrate. The die support includes lateral coupling paths between at least a portion of the embedded topside substrate pads and lateral topside pads on a topside surface of the die support lateral to the die area. The contactable TSV tips are contacted with probes to provide a first topside connection to the TSVs, and the lateral topside pads are contacted with probes to provide a second topside connection. Dual-side testing across the electronic assembly is performed using the first and second topside connections.

Lateral coupling enabled topside only dual-side testing of TSV die attached to package substrate

A method of testing electronic assemblies including singulated TSV die attached to a ML package substrate, on a substrate carrier. The substrate carrier includes through-holes for allowing probe contact to the BGA substrate pads on a bottomside of the package substrate that are coupled to the frontside of the TSVs. Contactable TSV tips on the bottomside of the TSV die are contacted with a topside coupler that includes a pattern of coupling terminals that matches a layout of at least a portion of the TSV tips or pads coupled to the TSV tips. The topside coupler electrically connects pairs of coupling terminals to provide a plurality of TSV loop back paths. The BGA substrate pads are contacted with a plurality of probes tips that extend through the through-holes to couple to the frontside of the TSVs. Electrical testing is performed across the electronic assembly to obtain at least one test parameter.

Through carrier dual side loop-back testing of TSV die after die attach to substrate

Disclosed herein are systems and methods for testing the functionality of a plurality of integrated circuit dies formed in a plurality of rows on a semiconductor wafer. In one embodiment, the system includes a probe device having at least two probing areas configured to test the functionality of the plurality of dies. The first probing area of the at least two probing areas is positioned to test each of a plurality of dies in a first row of the plurality of rows and a second probing area of the at least two probing areas is positioned to test each of a plurality of dies in a second row of the plurality of rows simultaneously with the first probing area. The system also includes a tester device coupled to the probe device and configured to compare test data received from the die in the first row with test data received from the die in the second row.

System and method for site-to-site yield comparison while testing integrated circuit dies

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Sachse, TX, United States of America

James L Oborny