Micron Technology Incorporated

James L Dale

David A Cathey

Richard H Lane

Fred D Fishburn

Hongmei Wang

Terrence B McDaniel

Rodney C Langley

William J Crane

Jeffrey V Musser

Eric A Powell

John C Freeman

Randall Culver

Methods to form contact openings and allow the formation of self-aligned contacts for use in the manufacture of semiconductor devices are described. During formation of a multi-layered resist, a hard mask material is introduced beneath an anti-reflective coating to be used as an etch stop layer. The multi-layered resist is patterned and etched, to transfer the desired contact pattern to a substrate material, such as a silicon substrate, to form contact openings therein. The contact openings provide for the formation of self-aligned contacts therein.

Methods of forming a contact opening in a semiconductor assembly using a disposable hard mask

An ion implanting method includes forming a pair of spaced and adjacent features projecting outwardly from a substrate. At least outermost portions of the pair of spaced features are laterally pulled away from one another with a patterned photoresist layer received over the features and which has an opening therein received intermediate the pair of spaced features. While such spaced features are laterally pulled, a species is ion implanted into substrate material which is received lower than the pair of spaced features. After the ion implanting, the patterned photoresist layer is removed from the substrate. Other aspects and implementations are contemplated.

Ion implanting methods

Extraneous and undesirable particulate matter is suppressed in a reaction chamber for treating semiconductor materials by depositing a thin layer of polymeric or equivalent insulating material over the entire interior surfaces of the reaction chamber prior to any treatment therein of semiconductor wafers or the like. This process is repeated as necessary after the initial treatment of the wafers has begun, and this treatment will typically include the layer deposition and layer etching on the surfaces of the semiconductor wafers. The periodic intervals between subsequent polymer layer deposition within the reaction chamber is selected in proportion to measured etch or deposition rates therein to thereby optimize the stability and uniformity of these etch and deposition rates, while simultaneously maintaining a maximum degree of cleanliness within the reaction chamber and minimizing down time therefor. The above control of particulate tack-down film deposition may be carried out using a novel closed loop control system in which etch and film deposition rates are measured to generate an error signal, and this error signal is used to control a gas flow controller which in turn regulates the frequency of tack-down film deposition within the reaction chamber.

Process and system for stabilizing layer deposition and etch rates while

A fluctuating voltage to be monitored is fed to the non-inverting input of a first op amp via a first input resistor; a reference voltage is fed to the inverting input of the second op amp via a second input resistor. The inverting input of the first op amp is taken from a first voltage divider connected between the reference voltage and ground; the non-inverting input of the second op amp is taken from a second voltage divider connected between the fluctuating voltage and ground. The power inputs of both op amps are connected to a positive voltage and ground. The output of both op amps is tied together, with a first feedback loop feeding the tied output voltage to the non-inverting input of the first op amp via a first high-resistance gain-setting resistor, and a second feedback loop feeding the tied output voltage to the inverting input of the second op amp via a second high-resistance gain-setting resistor. The range of acceptable values for the fluctuating voltage is established by selecting appropriate resistances for the resistors which comprise the pair of voltage dividers.

Voltage comparator circuit for monitoring a process output voltage

A plasma dry etch chamber is provided with an anode plate which has a cooling jacket which extends radially outwardly from a cooling core to an extent corresponding to the radial dimension of a silicon wafer work product. In order to further reduce deposit formation, the outer perimeter of the anode is designed to reduce the effects of polymer deposition.

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Boise, ID, United States of America

James L Dale