Texas Instruments Corporation

Other

North Carolina State University

James Joseph Chambers

Mark R Visokay

Luigi Colombo

Hiroaki Niimi

Antonio Luis Pacheco Rotondaro

Antonio L P Rotondaro

Brian Keith Kirkpatrick

Rajesh B Khamankar

Manuel A Quevedo-Lopez

Douglas Ticknor Grider

Amitabh Jain

Toan Tran

Leif Christian Olsen

April Gurba

Haowen Bu

Shaofeng Yu

Sunil V Hattangady

Ajith Varghese

Gregory N Parsons

M Jason Kelly

Anna Carin Cecilia Chambers

Freido Mehrad

A drinking container with an integrated valve that uses surface tension to control the flow of fluid.

Systems and methods associated with a drinking container with a solid, integrated valve

A process is disclosed of forming metal replacement gates for PMOS transistors with oxygen in the metal gates such that the PMOS gates have effective work functions above 4.85. Metal work function layers in the PMOS gates are oxidized at low temperature to increase their effective work functions to the desired PMOS range. Hydrogen may also be incorporated at an interface between the metal gates and underlying gate dielectrics. Materials for the metal work function layers and processes for the low temperature oxidation are disclosed.

Methods to enhance effective work function of mid-gap metal by incorporating oxygen and hydrogen at a low thermal budget

An integrated circuit containing metal replacement gates may be formed by forming a nitrogen-rich titanium-based barrier between a high-k gate dielectric layer and a metal work function layer of a PMOS transistor. The nitrogen-rich titanium-based barrier is less than 1 nanometer thick and has an atomic ratio of titanium to nitrogen of less than 43:57. The nitrogen-rich titanium-based barrier may be formed by forming a titanium based layer over the gate dielectric layer and subsequently adding nitrogen to the titanium based layer. The metal work function layer is formed over the nitrogen-rich titanium-based barrier.

High-K metal gate

A process is disclosed of forming metal replacement gates for NMOS and PMOS transistors with oxygen in the PMOS metal gates and metal atom enrichment in the NMOS gates such that the PMOS gates have effective work functions above 4.85 eV and the NMOS gates have effective work functions below 4.25 eV. Metal work function layers in both the NMOS and PMOS gates are oxidized to increase their effective work functions to the desired PMOS range. An oxygen diffusion blocking layer is formed over the PMOS gate and an oxygen getter is formed over the NMOS gates. A getter anneal extracts the oxygen from the NMOS work function layers and adds metal atom enrichment to the NMOS work function layers, reducing their effective work functions to the desired NMOS range. Processes and materials for the metal work function layers, the oxidation process and oxygen gettering are disclosed.

Structure and method for metal gate stack oxygen concentration control using an oxygen diffusion barrier layer and a sacrificial oxygen gettering layer

The likelihood of forming silicon germanium abnormal growths, which can be undesirably formed on the gate electrode of a strained-channel PMOS transistor at the same time that silicon germanium source and drain regions are formed, is substantially reduced by using protection materials that reduce the likelihood that the gate electrode is exposed during the formation of the silicon germanium source and drain regions.

Method of substantially reducing the formation of SiGe abnormal growths on polycrystalline electrodes for strained channel PMOS transistors

A method of forming an integrated circuit (IC) having at least one MOS device includes forming a SiON gate dielectric layer on a silicon surface. A gate electrode layer is deposited on the SiON gate layer and then patterning forms a gate stack. Exposed gate dielectric sidewalls are revealed by the patterning. A supplemental silicon oxide layer is formed on the exposed SiON sidewalls followed by nitriding. After nitriding, a post nitridation annealing (PNA) forms an annealed N-enhanced SiON gate dielectric layer including N-enhanced SiON sidewalls, wherein along lines of constant thickness a N concentration at the N-enhanced SiON sidewalls is &#x2267; the N concentration in a bulk of the annealed N-enhanced SiON gate layer &#x2212;2 atomic %. A source and drain region on opposing sides of the gate stack are formed to define a channel region under the gate stack.

MOS transistors including SiON gate dielectric with enhanced nitrogen concentration at its sidewalls

An integrated circuit (IC) includes a substrate having a top semiconductor surface including at least one MOS device including a source and a drain region spaced apart to define a channel region. A SiON gate dielectric layer that has a plurality of different N concentration portions is formed on the top semiconductor surface. A gate electrode is on the SiON layer. The plurality of different N concentration portions include (i) a bottom portion extending to the semiconductor interface having an average N concentration of &#x3c;2 atomic %, (ii) a bulk portion having an average N concentration &#x3e;10 atomic %, and (iii) a top portion on the bulk portion extending to a gate electrode interface having an average N concentration that is &#x2267;2 atomic % less than a peak N concentration of the bulk portion.

Semiconductor device including SiON gate dielectric with portions having different nitrogen concentrations

A CMOS device having an NMOS transistor with a metal gate electrode comprising a mid-gap metal with a low work function/high oxygen affinity cap and a PMOS transistor with a metal gate electrode comprising a mid gap metal with a high work function/low oxygen affinity cap and method of forming.

Method for dual work function metal gate CMOS with selective capping

The invention provides a method for manufacturing a semiconductor device that comprises placing a metallic gate layer over a gate dielectric layer where the metallic gate layer has a crystallographic orientation, and re-orienting the crystallographic orientation of the metallic gate layer by subjecting the metallic gate layer to a hydrogen anneal.

Growing community of inventors

Dallas, TX, United States of America

James Joseph Chambers