Freescale Semiconductor,inc.

James J Wang

William G McDonald

Alan J Magnus

Justin Eugene Poarch

Methods are provided for forming Quad Flat No-Lead (QFN) packages. An embodiment includes disposing an active side of a semiconductor chip on a plurality of leads, coupling a plurality of wire bonds to the active side of the semiconductor chip, coupling the plurality of wire bonds to the plurality of leads in a space between the active side and the plurality of leads, and encasing the semiconductor chip, at least a portion of each of the plurality of leads, and the plurality of wire bonds in a mold material to define a mounting side of the QFN package. The mounting side has a perimeter, the plurality of leads are oriented on and exposed on the mounting side within the perimeter, and the plurality of wire bonds are oriented between the active side and the mounting side within the mold material.

Methods for forming quad flat no-lead (QFN) packages

Quad Flat No-Lead (QFN) packages are provided. An embodiment of a QFN package includes a semiconductor chip including an active surface and an inactive surface, a plurality of leads, a plurality of wire bonds configured to couple the plurality of leads to the semiconductor chip, and a mold material including a mounting side and having a perimeter. The active surface is oriented toward the mounting side, the plurality of wire bonds are disposed between the active surface and the mounting side within the mold material, and the plurality of leads are exposed on the mounting side and are at least partially encapsulated within the perimeter of the mold material.

Quad flat no-lead (QFN) packages

Methods and apparatus are provided for decreasing the size of Quad Flat No-Lead (QFN) packages () down to chip-scale packages. Such QFN packages include a first semiconductor chip (), a plurality of recessed leads () having mold lock features, and a mold materialsubstantially encasing all sides of the semiconductor chip. An active surface () of the semiconductor chip is oriented toward a mounting side () of the QFN package, and a plurality of wire bondsdisposed between the active surface and the mounting side couple the active side to the leads. The QFN packages may also include a second semiconductor chip () coupled to a plurality of leads () and to the first semiconductor chip via wire bonds () in a manner similar to the first semiconductor chip.

Methods and apparatus for a Quad Flat No-Lead (QFN) package

One embodiment relates to using a robust metal layer of a semiconductor device to form landing pads. In one embodiment, a sputterable, nonwettable refractory metal is used as a solder mask for the landing pads. A second device may then be coupled to the robust metal layer landing pads of the semiconductor device. In one embodiment, the landing pads are formed while the semiconductor device is in wafer form, and a second device is then coupled to the landing pads of each of the plurality of semiconductor devices within the wafer, such that each semiconductor device within the wafer is electrically coupled to a second device. In this manner, each semiconductor device within the wafer and its corresponding second device may be probed and tested as a system. After probing and testing, the wafer may be singulated into a plurality of individual device assemblies which may then be packaged.

Growing community of inventors

Phoenix, AZ, United States of America

James J Wang