International Business Machines Corporation

James J Quinlivan

Beth A Ward

James Spiros Nakos

Jay Sanford Burnham

Steven M Shank

Arne Watson Ballantine

Jeffrey D Gilbert

Kevin K Chan

Glen L Miles

Samuel C Ramac

Michael B Rice

Kevin M Houlihan

John J Ellis-Monaghan

Paul Charles Jamison

Christopher Peter D'Emic

Mukesh Vijay Khare

Deborah A Tucker

Thomas T Hwang

Bernie Roque, Jr

Alvin Jose Joseph

Xuefeng Liu

James Albert Slinkman

Jeffrey Scott Brown

Peter John Geiss

Anthony C Speranza

A method of fabricating a gate dielectric layer. The method includes: providing a substrate; forming a silicon dioxide layer on a top surface of the substrate; performing a plasma nitridation in a reducing atmosphere to convert the silicon dioxide layer into a silicon oxynitride layer. The dielectric layer so formed may be used in the fabrication of MOSFETs.

Method for fabricating a nitrided silicon-oxide gate dielectric

A method of fabricating a semiconductor structure. The method includes forming a first feature of a first active device and a second feature of a second active device, introducing a first amount of nitrogen into the first feature of the first active device, and introducing a second amount of nitrogen into the second feature of the second active device, the second amount of nitrogen being different from the first amount of nitrogen.

Selective nitridation of gate oxides

Polysilicon electrical depletion in a polysilicon gate electrode is reduced by depositing the polysilicon under controlled conditions so as to vary the crystal grain size through the thickness of the polysilicon. The resulting CMOS transistor may have two or more depth-wise contiguous regions of respective crystalline grain size, and the selection of grain size may be directed to maximize dopant activation in the polysilicon near the gate dielectric and to tailor the resistance of the polysilicon above that first region and more distant from the gate dielectric. A region of polycrystalline silicon may have a varying grain size as a function of a distance measured from a surface of the dielectric film.

CMOS transistor with a polysilicon gate electrode having varying grain size

A method of fabricating a gate dielectric layer, including: providing a substrate; forming a silicon dioxide layer on a top surface of the substrate; performing a plasma nitridation in a reducing atmosphere to convert the silicon dioxide layer into a silicon oxynitride layer. The dielectric layer so formed may be used in the fabrication of MOSFETs.

A semiconductor structure includes thin gate dielectrics that have been selectively nitrogen enriched. The amount of nitrogen introduced is sufficient to reduce or prevent gate leakage and dopant penetration, without appreciably degrading device performance. A lower concentration of nitrogen is introduced into pFET gate dielectrics than into nFET gate dielectrics. Nitridation may be accomplished selectively by various techniques, including rapid thermal nitridation (RTN), furnace nitridation, remote plasma nitridation (RPN), decoupled plasma nitridation (DPN), well implantation and/or polysilicon implantation.

A method for forming a gate dielectric for an integrated circuit device. In an exemplary embodiment of the invention, the method includes forming an initial oxynitride layer upon a substrate material, the oxynitride layer having an initial physical thickness. The initial oxynitride layer is then subjected to a plasma nitridation, the plasma nitridation resulting in final oxynitride layer having a final physical thickness.

Nitrided ultra thin gate dielectrics

A method for removing silicon dioxide residuals is disclosed. The method includes reacting a portion of a silicon dioxide layer (i.e., oxide) to form a reaction product layer, removing the reaction product layer and annealing in an environment to remove oxide residuals. The method finds application in a variety of semiconductor fabrication processes including, for example, fabrication of a vertical HBT or silicon-to-silicon interface without an oxide interface.

Silicon dioxide removing method

Methods such as Remote Plasma Nitridation (RPN) are used to introduce nitrogen into a gate dielectric layer. However, these methods yield nitrided layers where the layers are not uniform, both in cross-sectional profile and in nitrogen profile. Subjecting the nitrided layer to an additional NO anneal process increases the uniformity of the nitrided layer.

Thermal nitrogen distribution method to improve uniformity of highly doped ultra-thin gate capacitors

Method for improved plasma nitridation of ultra thin gate dielectrics

Polysilicon electrical depletion in a polysilicon gate electrode is reduced by depositing the polysilicon under controlled conditions so as to vary the crystal grain size through the thickness of the polysilicon. The resulting structure may have two or more depth-wise contiguous regions of respective crystalline grain size, and the selection of grain size is directed to maximize dopant activation in the polysilicon near the gate dielectric, and to tailor the resistance of the polysilicon above that first region and more distant from the gate dielectric. This method, and the resulting structure, are advantageously employed in forming FETs, and doped polysilicon resistors.

Method of reducing polysilicon depletion in a polysilicon gate electrode by depositing polysilicon of varying grain size

A structure comprising a trench having a liner with rounded corners in the top and bottom of the trench is obtained by rapid thermal oxidation.

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Essex Junction, VT, United States of America

James J Quinlivan