Intel Corporation

Intel Corportion

James Edward Neeb

Bradly L Inman

Nathan S Blackwell

James G Maveety

John C Johnson

Abram M Detofsky

Nader N Abazarnia

Jeffrey H Luke

Shelby G Rollins

Sundar V Pathy

Pramod Malatkar

Christopher J Nelson

Hemanth K Dhavaleswarapu

Yu Amos Zhang

Timothy J Callahan

Stephen Sturges

Jared Pager

Hiren V Tilala

Jesse Armagost

Matthew Boelter

Matthew Hendricks

Geoffrey Kelly

Embodiments described herein may be directed to receiving a plurality of data captured, respectively, by a plurality of test instruments coupled to a device under test, wherein a plurality of data elements within, respectively, the plurality of captured data are associated with a timestamp based upon a time a data element was captured. Embodiments may also analyze the received plurality of data captured, respectively, by the one or more test instruments, and graphically display at least a portion of the analyzed plurality of captured data to a user. Other embodiments may be identified herein.

Debug tool for test instruments coupled to a device under test

Embodiments herein relate to apparatus, systems, and methods to compress a test pattern onto a field programmable gate array to test a device under test. This may include identifying values of a plurality of drive pins for a plurality of test cycles to apply to an input of the DUT for each of the plurality of test cycles, identifying values of a plurality of compare pins for the plurality of test cycles to compare an output of the DUT, respectively, for each of the plurality of test cycles, analyzing the identified values, compressing, based on the analysis, the values of the plurality of drive pins and the plurality of compare pins, and storing the compressed values on the FPGA.

Compressed test patterns for a field programmable gate array

Techniques and configurations are disclosed herein for communication between devices. In some embodiments, a bus for communication between first and second devices may include a transmit buffer and one or more processing devices. The one or more processing devices may be configured to receive first asynchronous data from an operating system, running on a central processing unit of the first device, on an operating system signal path; transmit the first asynchronous data from the first device to the second device on a command signal path; transmit first data from the transmit buffer to the second device at a first fixed packet frequency on a transmit signal path; and receive data from the second device at a second fixed packet frequency on a receive signal path different from the transmit signal path. Other embodiments may be disclosed and/or claimed.

Bus for communication between devices

A thermal controller includes a thermal control interface to receive test data from an automated test equipment (ATE) system and dynamically adjust a target setpoint temperature based on the data and a dynamic thermal controller to receive the target setpoint temperature from the thermal control interface and control a thermal actuator based on the target setpoint temperature.

Integrated circuit test temperature control mechanism

Embodiments of a thermal compression bonding process bond head and a method for producing a thermal compression bonding process bond head are disclosed. In some embodiments, the bond head includes a thermal compression bonding process heater and a cooling block coupled to the heater through an annular structure. The annular structure surrounds a lower portion of the cooling block and couples the cooling block to the heater such that there is no direct mechanical contact between the cooling block and the heater.

Reduced expansion thermal compression bonding process bond head

Asynchronous communication between devices

A connector assembly is disclosed and claimed. The connector assembly includes a connector and a cable attachable at one end to the connector. The cable includes a first conductive layer and a second conductive layer disposed over the first conductive layer. A layer of insulation material is disposed at least between the first conductive layer and the second conductive layer and a plurality of capacitors are connected between the first conductive layer and the second conductive layer.

Connector assembly with decoupling capacitors

A JTAG tester includes a JTAG controller in a PCI slot of a PC, a port multiplexer, a programmable power supply, and drive and compare logic, which tracks V . The tester reads and blows information and configuration fuses on the silicon using the JTAG port. The tester pipes the JTAG port into a 1-to-N multiplexer, where N is the number of sockets being tested in parallel. The multiplexer is different from conventional multiplexers in that it allows selection of any combination of sockets, not just any one of the N sockets. Thus the same data can be driven into any combination of devices for parallel programming of fuse registers. Data being read out is read one device for separate evaluation via the single port back to the controller PC.

Joint test action group (JTAG) tester, such as to test integrated circuits in parallel

Multiple devices can be tested simultaneously for power continuity or for other power performance characteristic(s). If any of the devices have short circuit defects, for example, the fuse devices connected between these defective devices and a single power supply restrict the amount of current drawn by the defective devices. This allows power continuity testing to continue for all of the other devices. At the same time, the reduced voltage level of the defective devices, caused by the restriction of current by their corresponding fuse device, can be detected by the voltage measurement device. The reduced voltage levels allow the defective devices to be identified by a test control apparatus and to be excluded from subsequent testing.

Apparatus and method for power continuity testing in a parallel testing system

An integrated circuit provides self-heating in order to assist an externally applied thermal control unit raise the temperature of the integrated circuit to a specified range of temperatures at which functional testing is conducted. In a particular embodiment of the present invention, a packaged integrated circuit that is thermally coupled to a heat dissipating device, including but not limited to a heat sink, is operated in a high power manner prior to functional testing, so as to quickly raise internal junction temperatures to a specified test range before functional testing begins.

Growing community of inventors

Chandler, AZ, United States of America

James Edward Neeb