Cypress Semiconductor Corporation

Vlsi Technology, Inc.

General Signal Corporation

James E Nulty

Usha Raghuram

Christopher John Petti

James A Hunter

Chan-Lon Yang

Bo Jin

Jianmin Qiao

Daniel J Arnzen

Alexander J Herrera

Kimberley A Kaufman

Calvin T Gabriel

Siamak Salimian

Brenor L Brophy

Manuj Rathor

Thurman John Rodgers

E John Vowles

Sanjay M Thekdi

Pamela Shiell Trammel

Tinghao Frank Wang

Paul Arleo

Qi Gu

John O Torode

Jianmin Oiao

Howard S Kurasaki

Barbara F Westlund

Thomas A McCleary

A probe card for testing dice on a wafer includes a substrate, a number of cantilevers formed on a surface thereof, and a number of probes extending from unsupported ends of the cantilevers. The unsupported ends of the cantilevers project over cavities on the surface of the substrate. The probes have tips to contact pads on the dice under test. The probe card may include a compressive layer above the surface of the substrate with a number of holes through which the probes extend.

Method of fabricating a probe card

In one embodiment, a probe card for testing dice on a wafer includes a substrate, a number of cantilevers formed on a surface thereof, and a number of probes extending from unsupported ends of the cantilevers. The unsupported ends of the cantilevers project over cavities on the surface of the substrate. The probes have tips to contact pads on the dice under test. The probe card may include a compressive layer above the surface of the substrate with a number of holes through which the probes extend.

Probe card and method for constructing same

In one embodiment, an anti-wafer structure includes a silicon on insulator (SOI) layer and a plurality of probe dice formed on the SOI layer. Each of the probe die may have a pad layout corresponding to a pad layout of a die on a wafer under test. A plurality of holes may extend through the SOI layer and the plurality of probe dice, with each hole corresponding to a pad on a probe die. The anti-wafer structure may be advantageously used in an advanced probe card. Techniques for fabricating an anti-wafer and an advanced probe card are also disclosed.

Advanced probe card and method of fabricating same

Prior to etching a poly-II layer during fabrication of an integrated circuit, a hydrofluoric acid (HF) dip is used to remove surface oxides from the poly-silicon layer and an anisotropic descumming operation is used to remove any resist material left over from a patterning operation. Following patterning, a long breakthrough etch (e.g., sufficient to remove 300-1500 &#x212b; of oxide) using an anisotropic breakthrough etchant (e.g., a fluorocarbon-based etchant) is performed before the poly-silicon layer is etched. The HF dip may be repeated if a predetermined time between the first dip and the etch is exceeded. The anisotropic descumming operation may be performed using an anisotropic anti-reflective coating (ARC) etch, e.g., a Cl/O, HBr/O, CF/Oor another etch having an etch rate of approximately 3000 &#x212b;/min for approximately 10-20 seconds. The poly-silicon layer may be annealed following (but not prior to) the etch thereof.

Method for etching and/or patterning a silicon-containing layer

In one embodiment, an environment for testing integrated circuits includes a first die coupled to a tester. The first die includes a removable connection configured to couple a signal from the first die with an adapter layer to a second die being tested. The removable connection may be an elastomeric interposer or a probe, for example.

Probe card with an adapter layer for testing integrated circuits

A process for minimizing lateral spacer erosion of an insulating layer adjacent to a contact region and an apparatus whereby there is provided a contact opening with a small alignment tolerance relative to a gate electrode or other structure are disclosed. The process includes the steps of forming a conductive layer on a semiconductor body, then depositing an insulating layer adjacent to the conductive layer. Next, substantially rectangular insulating spacers are formed adjacent to the gate electrode. An etch stop layer is deposited adjacent the insulating layer, followed by an etch to remove the etch stop layer material from the contact region. This etch is conducted under conditions wherein the etch removes the etch stop layer, but retains the substantially rectangular lateral spacer profile of the first insulating layer. The apparatus is capable of maintaining high quality contacts between the conductive material in the contact region and an underlying device region such as a source or drain, or some other layer or structure, and is an effective structure for small feature size structures, particularly self-aligned contact structures.

Structure having reduced lateral spacer erosion

The present invention relates to a method of plasma etching and a method of operating a plasma etching apparatus in which a concentration of oxygen at flash striking is greater than a concentration during etching.

Plasma etching method

An electrostatic or mechanical chuck assembly includes gas inlets only in an annulus-shaped peripheral portion and not in the central region of the chuck. The gas inlets are in fluid communication with one or more gas conduits and supply of the backside of a workpiece, such as a semiconductor wafer, with inert coolant gas or gases. The gas or gases supplied only to the peripheral region of the chuck effectively cool the central region of the chuck by at least two physical mechanisms, including the thermal conduction through the workpiece and diffusion of the gas or gases in the interstitial space(s) between the somewhat irregular facing surfaces of the chuck and of the backside of the workpiece.

ELECTROSTATIC OR MECHANICAL CHUCK ASSEMBLY CONFERRING IMPROVED TEMPERATURE UNIFORMITY ONTO WORKPIECES HELD THEREBY, WORKPIECE PROCESSING TECHNOLOGY AND/OR APPARATUS CONTAINING THE SAME, AND METHOD(S) FOR HOLDING AND/OR PROCESSING A WORKPIECE WITH THE SAME

A plasma etch chemistry and etch methodology is provided to improve critical dimension control for openings formed into and/or through a semiconductor thin film. According to an embodiment, the plasma etch chemistry includes an etchant mixture comprising a first etchant of the formula C H F (where x&gE;2, y&gE;1 and z&gE;2) and a second etchant other than the first etchant to form the openings. The relationship of x, y and z may be such that y&plus;z equals an even number &lE;2x&plus;2. According to an alternative embodiment, the plasma etch chemistry further includes strained cyclic (hydro)fluorocarbon. The plasma etch chemistry may be used to form openings in the layer in a single-etch step. In a further embodiment, the plasma etch chemistry described herein may etch less than the entire thickness of the layer, and a second plasma etch chemistry substantially free of the first etchant and strained cyclic (hydro)fluorocarbons etches the remainder of the layer to form the openings. Such an etch methodology advantageously reduces the risk of etching the materials underlying the layer.

Plasma etch chemistry and method of improving etch control

According to one embodiment (,), a method of forming contacts may include forming structures that include sidewalls (,). A first insulating layer can be deposited (,). A second insulating layer can then be deposited over the first insulating layer (,). The second insulating layer can be patterned to form a hard etch mask (,). Contact holes can be etched through the second insulating layer using the hard etch mask as a contact hole etch mask (,). A second insulating layer can have a dielectric constant that is low with respect to other hard etch mask materials, such as silicon nitride. A hard etch mask formed from a second insulating layer can result in contact holes having lower aspect ratios than conventional approaches.

Method and structure for making self-aligned contacts

The present invention relates to a method of plasma etching and a method of operating a plasma etching apparatus.

A process for minimizing lateral spacer erosion of an insulating layer adjacent to a contact region and an apparatus whereby there is provided a contact opening with a small alignment tolerance relative to a gate electrode or other structure are disclosed. The process includes the steps of forming a conductive layer on a semiconductor body, then depositing an insulating layer adjacent to the conductive layer. Next, substantially rectangular insulating spacers are formed adjacent to the gate electrode. An etch stop layer is deposited adjacent the insulating layer, followed by an etch to remove the etch stop layer material from the contact region. This etch is conducted under conditions wherein the etch removes the etch stop layer, but retains the substantially rectangular lateral spacer profile of the first insulating layer. The apparatus is capable of maintaining high quality contacts between the conductive material in the contact region and an device region, such as a source or drain, or some other layer or structure, and is an effective structure for small feature size structures, particularly self-aligned contact structures.

Method for eliminating lateral spacer erosion on enclosed contact

A method of etching an oxide layer is disclosed. First, a resist layer is formed on an oxide layer on a substrate. Next, a photosensitive layer is formed on the oxide layer and patterned to expose regions of the oxide layer to be removed. The exposed regions may overlie a nitride layer, and may overlie a structure such as a polysilicon gate. The etch is performed such that polymer deposits on the photosensitive layer, thus eliminating interactions between the photosensitive layer and the plasma. In this way, a simple etch process allows for good control of the etch, resulting in reduced aspect ratio dependent etch effects, high oxide:nitride selectivity, and good wall angle profile control.

Method of etching an oxide layer

A method of etching openings in oxide layers is disclosed. A hard mask layer is formed on the oxide layer. The hard mask layer is then patterned by a photoresist layer and an etch is performed to form openings in the hard mask. Next, the patterning layer may be removed and an etch is performed to remove the oxide in the regions defined by the hard mask layer openings. The etch with hard mask has minimized aspect ratio dependency, so that openings of different sizes may be formed simultaneously. An etch that may be carried out with Freon 134a (C.sub.2 H.sub.2 F.sub.4) to provide superior oxide:nitride selectivity is also disclosed. Additionally, the etch may be carried out at high temperature for improved wall profile without loss of selectivity. For deep openings, a two step etch process is disclosed, with a polymer clean step between the etches to remove polymer build up from first etch, and allow the etch to proceed to an increased depth.

A method for forming a stable plasma, particularly in the high power and low pressure ranges. The method may be used in a plasma system such as that used for a plasma etch. First, the radio frequency power is turned on under low power and high pressure. The plasma is allowed to stabilize without tuning. Next, the pressure is dropped to the desired operating level and the tuning system is engaged. After tuning at the low power and low pressure, the radio frequency power is ramped to the desired level. Finally, the system is again tuned at the higher power.

Growing community of inventors

San Jose, CA, United States of America

James E Nulty