Motorola Corporation

Freescale Semiconductor,inc.

James E Drye

David J Reed

Earl K Davis

Vern H Winchell, Ii

Jack A Schroeder

Steven L Post

Scott M Hayes

Jinbang Tang

Debabrata Gupta

Shun Meen Kuo

Lih-Tyng Hwang

A method for mini module EMI shielding effectiveness evaluation comprises providing a test vehicle including at least one test platform. The test platform includes at least one mini emitter, a mini receiver with a reference shield, and a mini receiver with a shield under test. EMI shielding effectiveness transmission signals are applied to the at least one mini emitter. Signals received by the mini receiver with a shield under test and the mini receiver with the reference shield are evaluated. The mini emitter, mini receiver with the reference shield, and mini receiver with the shield under test comprise components fabricated concurrently and under fabrication conditions used for fabrication of the test platform of the test vehicle. As used herein, a mini emitter and mini receiver may be interchanged according to the requirements of a given EMI shielding effectiveness evaluation.

Method and apparatus for mini module EMI shielding evaluation

A semiconductor device for multiple dice is provided that reduces insertion loss and return loss. In an example embodiment, the semiconductor device comprises: a packagecomprising a mount surfaceto which diceandare mounted, and a bond pad surfacedefining at least a first die areaand a second die areawherein the second die areais different in form from the first die area

Multiple dice package

A multi-chip module (26) used to interconnect and house a plurality of integrated circuits (10). The module (26) employs an intermediate structure referred to, herein, as a bridge chip (12). The bridge chip (12) connects the integrated circuit (10) to the module substrate (19). The integrated circuit (10) is attached to the bridge chip (12) and forms a composite structure (18) which can be burned-in and tested as an individual unit. The bridge chip (12) has interconnects to bring out the inputs and outputs of the integrated circuit (10). The composite structure (18) is mounted to the module substrate (19) such that, the integrated circuit (10) has a thermal pathway to the module substrate (19), and the bridge chip (12) connects to the module substrate (19). The module substrate (19) has interconnects to connect the plurality of composite structures (18).

Multiple integrated circuit module which simplifies handling and testing

A non-oxide ceramic (16) for electronic packages and a method of producing electronic packages using a non-oxide ceramic is provided. In accordance with the present invention, the non-oxide ceramic (16) is coated with silicon dioxide (15) and a bonding glass (14) having diboron trioxide is used to attach other package components such as semiconductor chips (18), leadframes (13), and heatsinks (11) to the non-oxide ceramic (16).

Electronic package having a non-oxide ceramic bonded to metal and method

A multichip IC module having dice and substrates coplanarly bonded therein. After the dice are aligned into die openings of the substrate, a glass slurry is applied and the module is fired to solidify the glass. Because of shrinkage of the glass slurry firing, a groove results between the dice and the substrate. To fill on this groove, a polyimide or like film is adhered and then pressued and cured on the surface of the dice and substrate. This film is used as a base for interconnect lines.

Multichip IC module having coplanar dice and substrate

An improved semiconductor die bonding structure and method for electrical devices is described which utilizes a ductile foil between the semiconductor die and the base of the device package. The die is sealed to the foil with a die bonding material formed from a titania free base glass to which has been added 23.6 to 36.4 weight percent lead titanate powder to give a glass plus ceramic mixture consisting essentially of (by weight percent) 2.5-10.7% GeO.sub.2, 0-2.3% SiO.sub.2, 58.6-78.5% PbO, 0-5.3% PbF.sub.2, 7-13% B.sub.2 O.sub.3, 2.5-6.9% Al.sub.2 O.sub.3, 0-5.3% ZnO, 0.4-2.3% V.sub.2 O.sub.5, 0-5.3% CdO, and 6.2-9.6% TiO.sub.2. The ductile foil is bonded to the ceramic package base directly without intermediate layers or alternatively by means of an improved foil bonding glass material consisting essentially of (by weight percent) 10-15% SiO.sub.2, 45-55% PbO, 8-12% ZnO, 2-5% Al.sub.2 O.sub.3, and 25-30% B.sub.2 O.sub.3.

Glass bonding means and method

A method for bonding die to substrates coplanarly in a multichip module assembly. After the die are aligned into die openings of the substrate, a glass slurry is applied and the module is fired to solidify the glass. Because of shrinkage of the glass slurry firing, a groove results between the die and the substrate. To fill on this groove, a polyimide or like film is adhered and then pressed and cured on the surface of the die and substrate. This film is used as a base for interconnect lines.

Coplanar die to substrate bond method

An electronic module having a high density of silicon IC chips is provided by mounting the chips in tapered through-holes in a silicon substrate, filling the edge gaps between the chips and the substrate with a glass so that the chips, the filler glass, and the substrate have a smooth upper surface adapted to receive monolithic interconnections formed by planar metalization methods. The resulting assembly is enclosed in a housing also formed substantially from silicon, which contains electrically isolated pins for contacting the input-output electrodes of the assembly. Preferential etching is used to form the through-holes in the substrate as well as various alignment means on the substrate and other parts of the housing so that they are self-aligning during assembly. Improved performance, reliability, and low cost is obtained.

Method of making a high density IC module assembly

An electronic module having a high density of silicon IC chips is provided by mounting the chips in tapered through-holes in a silicon substrate, filling the edge gaps between the chips and the substrate with a glass so that the chips, the filler glass, and the substrate have a smooth upper surface adapted to receive monolithic interconnections formed by planar metallization methods. The resulting assembly is enclosed in a housing also formed substantially from silicon, which contains electrically isolated pins for contacting the input-output electrodes of the assembly. Preferential etching is used to form the through-holes in the substrate as well as various alignment means on the substrate and other parts of the housing so that they are self-aligning during assembly. Improved performance, reliability, and low cost is obtained.

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Mesa, AZ, United States of America

James E Drye