Intel Corporation

James Chris Matayabas, Jr

Nachiket R Raravikar

Paul A Koning

Stephen Edward Lehman, Jr

Randall D Lowe, Jr

Saikumar Jayaraman

Ashay A Dani

Tian-An Chen

Lakshmi Supriya

Syadwad Jain

Nirupama Chakrapani

Gudbjorg H Oskarsdottir

Hitesh Arora

Akshay Mathkar

Robert L Sankman

Omkar G Karhade

Ravindranath Vithal Mahajan

Leonel R Arana

Sabina J Houle

Christopher L Rumer

Nisha Ananthakrishnan

Yiqun Bai

Arjun Krishnan

Suriyakala Ramalingam

Mitesh C Patel

Johanna M Swan

Adel A Elsherbini

Shawna M Liff

Feras Eid

Telesphor Kamgaing

Debendra Mallik

Sasha N Oster

Kemal Aygun

John Stephen Guzek

Nitin A Deshpande

Sanka Ganesan

Ram S Viswanath

Je-Young Chang

Daewoong Suh

Mitul Bharat Modi

Ravi V Mahajan

Edvin Cetegen

Dingying David Xu

Chung-Hao Chen

Zhimin Wan

Li-Sheng Weng

Manish Dubey

Charles A Gealer

Kyle Jordan Arrington

Rajen S Sidhu

Elah Bozorg-Grayeli

Aastha Uppal

Vijay Wakharkar

Hemanth K Dhavaleswarapu

Taylor W Gaines

Ken P Hackenberg

Elizabeth Nofen

Martha A Dudek

Wei Tan

Min Keen Tang

Timothy E McIntosh

Jinlin Wang

Kumar Abhishek Singh

Jan Krajniak

Nayandeep K Mahanta

Michelle S Phen

Yawei Liang

Marely E Tejeda Ferrari

Boxi Liu

David D Olmoz

An integrated circuit package includes a first die and second die above a substrate, and a vapor chamber above at least one of the first and second die. A vapor space within the vapor chamber is separated into at least a first section and a second section. The first section may be over the first die, and the second section may be over the second die, for example. The structure separating the first and second sections at least partly restricts flow of vapor between the first and second sections, thereby preventing or reducing thermal cross talk between the first and second dies. In some cases, an anisotropic thermal material is above one of the first or second die, wherein the anisotropic thermal material has substantially higher thermal conductivity in a direction of a heat sink than a thermal conductivity in a direction of a section of the vapor chamber.

Integrated heat spreader with enhanced vapor chamber for multichip packages

Microelectronic devices, assemblies, and systems include a microelectronic die and composite material to conduct heat from the microelectronic die such that the composite material includes polymer chains chemically bonded to fill particles having a hexagonal lattice of carbon atoms such as graphene sheet fill particles and/or carbon nanotube fill particles.

Carbon based polymer thermal interface materials with polymer chain to carbon based fill particle bonds

An apparatus is provided which comprises: a die comprising an integrated circuit, a first material layer comprising a first metal, the first material layer on a surface of the die, and extending at least between opposite lateral sides of the die, a second material layer comprising a second metal over the first material layer, and a third material layer comprising silver particles and having a porosity greater than that of the second material layer, the third material layer between the first material layer and the second material layer. Other embodiments are also disclosed and claimed.

Integrated heat spreader comprising a silver and sintering silver layered structure

An integrated circuit package may be formed having at least one heat dissipation structure within the integrated circuit package itself. In one embodiment, the integrated circuit package may include a substrate; at least one integrated circuit device, wherein the at least one integrated circuit device is electrically attached to the substrate; a mold material on the substrate and adjacent to the at least one integrated circuit device; and at least one heat dissipation structure contacting the at least one integrated circuit, wherein the at least one heat dissipation structure is embedded either within the mold material or between the mold material and the substrate.

Thermal management solutions for integrated circuit packages

In some embodiments a semiconductor die package includes a package substrate, a plurality of dies each attached to the package substrate, a layer of a thermally conducting sintered paste over the top of each die, a layer of flexible polymer thermal interface material over the sintered paste, and a heat spreader over and thermally connected to the polymer thermal interface material.

Multi-chip packages and sinterable paste for use with thermal interface materials

A microelectronic package may be fabricated with a microelectronic substrate, a microelectronic die electrically attached to the microelectronic substrate, and an electromagnetic interference shield layer contacting one or both of the microelectronic substrate and the microelectronic die, wherein the electromagnetic interference shield layer has an electrical conductivity between about 10,000 siemens per meter and 100,000 siemens per meter. The specific range of electrical conductivity results in electromagnetic fields either generated by the microelectronic die or generated by components external to the microelectronic package scattering within the electromagnetic interference shield layer and attenuating. Thus, the electromagnetic interference shield layer can prevent electromagnetic field interference without the need to be grounded.

Microelectronic package having electromagnetic interference shielding

Embodiments describe high aspect ratio and fine pitch interconnects for a semiconductor package, such as a package-on-package structure. In an embodiment, the interconnects are formed with a no-slump solder paste. In an embodiment, the no-slump solder paste is printed in an uncured state, and is then cured with a liquid phase sintering process. After being cured, the no-slump solder paste will not reflow at typical processing temperatures, such as those below approximately 400&#xb0; C. According to embodiments, the no-slump solder paste includes Cu particles or spheres, a solder matrix component, a polymeric delivery vehicle, and a solvent. In an embodiment, the liquid phase sintering produces a shell of intermetallic compounds around the Cu spheres. In an embodiment, the sintering process builds a conductive metallic network through the no-slump solder paste.

LPS solder paste based low cost fine pitch pop interconnect solutions

A multiple chip package is described with multiple thermal interface materials. In one example, a package has a substrate, a first semiconductor die coupled to the substrate, a second semiconductor die coupled to the substrate, a heat spreader coupled to the die, wherein the first die has a first distance to the heat spreader and the second die has a second distance to the heat spreader, a first filled thermal interface material (TIM) between the first die and the heat spreader to mechanically and thermally couple the heat spreader to the die, and a second filled TIM between the second die and the heat spreader to mechanically and thermally couple the heat spreader to the second die.

Multiple-chip package with multiple thermal interface materials

A polymer thermal interface material is described that has enhanced thermal conductivity. In one example, a vinyl-terminated silicone oil is combined with a silicone chain extender, and a thermally conductive filler comprising at least 85% by weight of the material, and comprising surface wetted particles with a range of shapes and sizes. The material may be used for bonding components inside a microelectronic package, for example.

Polymer thermal interface material having enhanced thermal conductivity

Flux formulations and solder attachment during the fabrication of electronic device assemblies are described. One flux formation includes a flux component and a metal particle component, the metal particle component being present in an amount of from 5 to 35 volume percent of the flux formulation. In one feature of certain embodiments, the metal particle component includes solder particles. Other embodiments are described and claimed.

Hybrid low metal loading flux

Space transformer including a substrate and a perforated plate disposed on the substrate. The substrate includes conductive traces and an array of conductive probe pins extend outwardly from anchor points on the substrate. The pins are electrically coupled to at least one of the conductive traces on the substrate as an interface between an E-testing apparatus and a DUT. The perforated plate may be affixed to a surface of the substrate and includes an array of perforations through which the conductive pins may pass. The perforated plate may provide one or more of lateral pin support and protection to the underlying substrate and/or traces. The perforated plate may include a metal sheet. A polymeric material may be disposed on at least a sidewall of the perforations to electrically isolate the metal sheet from the conductive probe pins.

Space transformer with perforated metallic plate for electrical die test

This disclosure relates generally to devices, systems, and methods for making a flexible microelectronic assembly. In an example, a polymer is molded over a microelectronic component, the polymer mold assuming a substantially rigid state following the molding. A routing layer is formed with respect to the microelectronic component and the polymer mold, the routing layer including traces electrically coupled to the microelectronic component. An input is applied to the polymer mold, the polymer mold transitioning from the substantially rigid state to a substantially flexible state upon application of the input.

Flexible electronic assembly method

Dendrimer/hyperbranched materials are combined with polyimide to form a low CTE material for use as a dielectric substrate layer or an underfill. In the alternative, ruthenium carbene complexes are used to catalyze ROMP cross-linking reactions in polyimides to produce a class of cross-linkable, thermal and mechanical stable material for use as a dielectric substrate or underfill. In another alternative, dendrimers/hyperbranched materials are synthesized by different methods to produce low viscosity, high Tg, fast curing, mechanically and chemically stable materials for imprinting applications.

Thermoset polymides for microelectronic applications

Methods for covalently and indelibly anchoring a polyacrylate polymer using a UV-induced polymerization process in the presence of a photoinitiator to an oxide surface are disclosed herein. The methods and compositions prepared by the methods can be used as indelible marking materials for use on microelectronic packages and as solder and sealant barriers to prevent overspreading of liquids on the oxide surfaces of microelectronic packages. The polyacrylate polymers are covalently linked to the oxide surface by use during the printing and UV-curing process of an adhesion promoter having as a first domain an oxide-reactive silyl group, bonded via a linker to an acrylate-reactive group.

Robust ink formulations for durable markings on microelectronic packages and its extendibility as a barrier material for thermal and sealant materials

Growing community of inventors

Chandler, AZ, United States of America

James Chris Matayabas, Jr