Mentor Graphics Corporation

Other

James C Word

Nicolas Bailey Cobb

Patrick Joseph LaCour

Yuri Granik

Kyohei Sakajiri

Konstantinos G Adam

Sergiy Komirenko

Michael Christopher Lam

Dragos S Dudau

Shady AbdelWahed

This application discloses a computing system to simulate a wafer image based on a mandrel mask and a block mask to be utilized to print a final wafer image on a substrate. To simulate the wafer image the computing system can estimate dummy sidewalls based on the mandrel mask, estimate contours of the block mask, and determine the simulated wafer image based on differences between the dummy sidewalls and the estimated contours of the block mask. The computing system can compare the simulated wafer image against a target wafer image in a layout design to identify hotspots where the simulated wafer image deviates from the target wafer image. Based on the identified hotspots, the computing system can modify the target wafer image in the layout design, prioritize edge modification in a subsequent optical proximity correction process, or modify computation of image error, which drives the optical proximity correction process.

Pattern correction in multiple patterning steps

A method of performing a resolution enhancement technique such as OPC on an initial layout description involves fragmenting a polygon that represents a feature to be created into a number of edge fragments. One or more of the edge fragments is assigned an initial simulation site at which the image intensity is calculated. Upon calculation of the image intensity, the position and/or number of initial simulation sites is varied. New calculations are made of the image intensity with the revised placement or number of simulation sites in order to calculate an OPC correction for the edge fragment. In other embodiments, fragmentation of a polygon is adjusted based on the image intensities calculated at the simulation sites. In one embodiment, the image intensity gradient vector calculated at the initial simulation sites is used to adjust the simulation sites and/or fragmentation of the polygon.

Fragmentation point and simulation site adjustment for resolution enhancement techniques

After layout design data has been modified using a resolution enhancement process, a repair flow is initiated. This repair flow includes checking a layout design altered by a resolution enhancement process for errors. A repair process is performed to correct detected sub-resolution assist feature errors. The repair process may employ a rule-based sub-resolution assist feature technique, a model-based sub-resolution assist feature technique, an inverse lithography-based sub-resolution assist feature technique, or any combination thereof.

Sub-resolution assist feature repair

Disclosed are techniques for simulating and correcting the mask shadowing effect using the domain decomposition method (DDM). According to various implementations of the invention, DDM signals for an extreme ultraviolet (EUV) lithography mask are determined for a plurality of azimuthal angles of illumination. Base on the DDM signals, one or more layout designs for making the mask may be analyzed and/or modified.

Simulation and correction of mask shadowing effect

After layout design data has been modified using an OPC process, a repair flow is initiated. This repair flow includes analyzing the modified data to identify any remaining or new potential print errors in the layout data. Regions then are formed around the identified potential print errors, and a subsequent OPC process is performed only on the data within these regions using a different set of process parameters from the process parameters employed by the initial OPC process. This repair flow is iteratively repeated, where a different set of process parameter values for the subsequent OPC process is used during each iteration.

Selective optical proximity layout design data correction

A system for creating mask layout pattern data in order to create a number of desired features on a semiconductor wafer. Critical features and features that are adjacent to or abut critical features are formed as phase shifting regions on a mask. Larger, non-critical features can be formed as annular rim shifters and may include one or more filling phase shifting regions. Non-critical features that are not adjacent to critical features and/or sub-resolution features that are not desired to print on the wafer can be formed as opaque or partially transparent regions on the mask.

Chromeless phase shifting mask for integrated circuits using interior region

A method for compensating for optical distortions occurring in regions associated with non-phase-shifting regions in a mask or reticle. OPC or other resolution enhancement techniques are performed on one or more edge segments associated with adjacent phase-shifting regions in order to compensate for edge position errors occurring in areas corresponding to non-phase-shifting regions.

Performing OPC on structures with virtual edges

A method and apparatus for compensating for flare intensity variations across an integrated circuit. A layout description for a physical layer of an integrated circuit or portion thereof is divided into a number of regions such as adjacent tiles. An estimate of the flare intensity in each region is determined. The flare intensity values calculated are divided into a number of ranges. In one embodiment, a data layer in a layout description is defined for each range of flare values computed. Features to be printed in an area having a flare value in a particular range are associated with a corresponding additional data layer. The features associated with each additional data layer are analyzed with a resolution enhancement technique that is selected or adjusted to compensate for differing flare values occurring in the integrated circuit.

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Portland, OR, United States of America

James C Word