Intel Corporation

James C Matayabas

Anna M Prakash

Carl L Deppisch

Edward Rudolph Prack

Ashay A Dani

Mukul P Renavikar

Rajen S Sidhu

Lilia May

Thomas J De Bonis

Srinivasa R Aravamudhan

Jason Jieping Zhang

Chang Lin

Nisha Ananthakrishnan

Arjun Krishnan

An apparatus is described that includes a substrate and a mold compound disposed on the substrate. The semiconductor die is embedded within the mold compound and is electrically coupled to lands on the substrate. Solder balls are disposed around the semiconductor die on the substrate. Each of the solder balls have a solid coating thereon. The solid coating contains a cleaning agent to promote its solder ball's coalescence with another solder ball. Respective vias are formed in the mold compound that expose the solder balls and their respective solid coatings. In combined or alternate embodiments outer edges of the mold compound have smaller thickness than regions of the mold compound between the vias and the semiconductor die. In combined or alternate embodiments micro-channels exist between the solder balls and the mold compound.

Package structure to enhance yield of TMI interconnections

Methods of forming microelectronic packaging structures and associated structures formed thereby are described. Those methods and structures may include forming a wafer level underfill (WLUF) material comprising a resin material, and adding at least one of a UV absorber, a sterically hindered amine light stabilizer (HALS), an organic surface protectant (OSP), and a fluxing agent to form the WLUF material. The WLUF is then applied to a top surface of a wafer comprising a plurality of die.

Methods of forming wafer level underfill materials and structures formed thereby

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Gilber, AZ, United States of America

James C Matayabas