USA as Represented by Secretary of the Navy

James C Gallagher

Travis J Anderson

Marko J Tadjer

Boris N Feigelson

Alan G Jacobs

Karl D Hobart

Michael Anthony Mastro

Jennifer K Hite

A computer-implemented method for evaluating a semiconductor wafer. In accordance with the present invention, using a properly designed neural network, the computer can take image data regarding the wafer at issue, plus image and electrical data regarding a prior wafer and devices fabricated on the prior wafer, to find relations to and between structural features, both known and previously unidentified, that can degrade the performance of devices fabricated on the wafer and/or can reduce the device yield of the wafer.

Neural network based prediction of semiconductor device response

A method for activating implanted dopants and repairing damage to dopant-implanted GaN to form n-type or p-type GaN. A GaN substrate is implanted with n- or p-type ions and is subjected to a high-temperature anneal to activate the implanted dopants and to produce planar n- or p-type doped areas within the GaN having an activated dopant concentration of about 10-10cm. An initial annealing at a temperature at which the GaN is stable at a predetermined process temperature for a predetermined time can be conducted before the high-temperature anneal. A thermally stable cap can be applied to the GaN substrate to suppress nitrogen evolution from the GaN surface during the high-temperature annealing step. The high-temperature annealing can be conducted under Npressure to increase the stability of the GaN. The annealing can be conducted using laser annealing or rapid thermal annealing (RTA).

GaN devices with ion implanted ohmic contacts and method of fabricating devices incorporating the same

A method for mapping and analyzing a GaN substrate to identify areas of the substrate suitable for fabrication of electronic devices thereon. Raman spectroscopy is performed over the surface of a GaN substrate to produce maps of the Eand Apeaks at a plurality of areas on the substrate surface, the Eand Apeaks being associated with known concentrations of defects and charge carriers, so that areas of the GaN substrate having relatively high resistivity or conductivity which make those areas suitable or unsuitable for fabrication of electronic devices can be identified. The devices can then be fabricated only on suitable areas of the substrate, or the size of the devices can be tailored to maximize the yield of devices fabricated thereon. Substrates not meeting a threshold level of defect and/or charge carrier concentration can be discarded without fabrication of poor-quality devices thereon.

Mapping and evaluating GaN wafers for vertical device applications

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Alexandria, VA, United States of America

James C Gallagher