Texas Instruments Corporation

James B Friedmann

Shawn T Walsh

Christopher C Baum

John E Campbell

Robert Kraft

Gregory Boyd Shinn

Reima Tapani Laaksonen

Sue E Crank

Joe G Tran

Ju-Ai Ruan

Wayne A Bather

Michelle L Hartsell

Jeffrey Loewecke

Troy A Yocum

Byron T Ahlburn

Brian M Trentman

Jaideep Mavoori

Somit Joshi

Shangting Detweiler

Yuqing Xu

Thomas M Parrill

Der'E Jan

Michael J McGranaghan

Janice D Makos

Arun Sivasothy

Kaneez E-shaher Banu

Joshua J Robbins

James D Vaughan

A silicon rich anti-reflective coating () is formed on a layer () in which narrow linewidth features are to be formed. Prior to the formation of a photoresist layer (), the anti-reflecting coating () is exposed to excited oxygen species to reduce photoresist poisoning.

Method to reduce photoresist poisoning

A method for determining the anti-reflective coating (or bottom anti-reflective coating) over-etch time adjust with real-time process feedback is presented. The critical dimension CDof the patterned photoresist is measured and a first wafer with median values chosen () from a lot. A first time t* is found () and used to form the desired structure. Using the measured critical dimension of the formed structure on the first wafer a second time tis found (). Finally, an over-etch time t(x) is found and used to etch the remaining wafers in the lot ().

Method for BARC over-etch time adjust with real-time process feedback

The present invention provides a method for manufacturing semiconductor devices, a method for manufacturing an integrated circuit, and a method for improving a drive current for semiconductor devices on a wafer-by-wafer basis. The method for manufacturing semiconductor devices, among other elements, includes patterning gate structures on a substrate (), each of the gate structures having a profile associated therewith, and obtaining information representative of the profiles of the gate structures (). In accordance with the present invention the information may then be fed forward to alter a manufacturing parameter associated with a drive current of the semiconductor devices ().

Method for improving a drive current for semiconductor devices on a wafer-by-wafer basis

A method for forming planar isolation structures for integrated circuits. A etch barrier is formed over the isolation fill material and an etch back is performed to remove material above unetched portions of the substrate. The exposed fill material is etched and planarized to form a planar isolation structure.

Shallow trench isolation planarization using self aligned isotropic etch

A process for forming a polysilicon line having linewidths below 0.23 &mgr;m. The layer of polysilicon ( ) is deposited over a semiconductor body ( ). A layer of bottom anti-reflective coating (BARC) ( ) is deposited over the polysilicon layer ( ). A resist pattern ( ) is formed over the BARC layer ( ) using conventional lithography (e.g., deep UV lithography). The BARC layer ( ) is etched with an etch chemistry of HBr/O using the resist pattern ( ) until the endpoint is detected. The BARC layer ( ) and resist pattern ( ) are then overetched using the same etch chemistry having a selectivity of approximately one-to-one between the BARC and resist. The overetch is a timed etch to control the linewidth reduction in the resist/BARC pattern. The minimum dimension of the pattern ( ) is reduced to below the practical resolution limit of the lithography tool. Finally, the polysilicon layer ( ) is etched using the reduced width pattern ( ).

Tunable gate linewidth reduction process

A method is given for removing excess oxide from active areas after shallow trench isolation, without the use of chemical-mechanical polishing. A nitride mask protects active areas during the etch of isolation trenches. The trenches are filled with oxide, using high density plasma deposition, which simultaneously etches, providing a sloping contour around the isolation trenches. A further layer of nitride is used to provide a cap over the trench which seals to the underlying layer of nitride. The cap layer of nitride receives a patterned etch to remove the cap only over the active areas. This allows a selective etch to remove the excess oxide, which can be followed by a selective etch to remove the nitride layers.

Method for trench isolation of semiconductor devices

Growing community of inventors

Dallas, TX, United States of America

James B Friedmann