Intel Corporation

Tahoe Research, Ltd.

James A McCall

Kuljit Singh Bains

Michael W Leddige

Christopher P Mozak

George Vergis

Chong J Zhao

Bill Nale

David N Shykind

Hing Yan To

Christopher E Cox

Xiang Li

Jun Liao

Aaron K Martin

Shigeki Tomishima

Bryan K Casper

Yunhui Chu

Michael Gutzmann

Rajat Agarwal

Pete D Vogt

Zhen Zhou

John R Goles

Jong-Ru Guo

Hing Thomas Y To

Robert J Friar

Kai Xiao

Randy B Osborne

Zuoguo Wu

Bryce D Horine

Mozhgan Mansuri

Suneeta Sah

Klaus J Ruff

Daqiao Du

Ge Chang

Hsien-Pao Yang

Derek M Conrow

Akshith Vasanth

Qin Li

Yan Fu

Wei P Chen

John B Halbert

Arvind A Kumar

Zhichao Zhang

Harry Muljono

Randy M Bonella

Jaejin Lee

Dimitrios Ziakas

Xiaoning Ye

Yidnekachew S Mekonnen

Joe Salmon

Ritesh B Trivedi

Santanu Chaudhuri

Jingbo Li

Chung Lam

Jim M Dodd

Brad Larson

Bruce A Christenson

Konika Ganguly

Dean-Dexter R Eugenio

Charles C Phares

Mo Liu

Zibing Yang

Tae-Young Yang

Michael Sandhinti

Ling Zheng

Changhong Lin

Clinton F Walker

Beomtaek Lee

Hing&ldquo;Thomas&rdquo; Y To

Steven M Stahlberg

Jose Angel Ramos Martinez

Rogelio Alfonso Moreyra Gonzalez

Yanjie Zhu

San K Chhay

Ajit Deosthali

Yuanhong Zhao

Kevin Stone

Byran K Casper

A memory subsystem includes multiple memory resources connected in parallel, including a first memory resource and a second memory resource. The memory subsystem can split a portion of data into multiple sub-portions. Split into smaller portions, the system needs fewer ECC (error checking and correction) bits to provide the same level of ECC protection. The portion of data can include N ECC bits for error correction, and the sub-portions can each include a sub-portion of (N−M) ECC bits for error correction. The system can then use M bits of data for non-ECC purposes, such as metadata.

Distribution of error checking and correction (ECC) bits to allocate ECC bits for metadata

A stack of memory chips and a logic chip is placed within a same package. Multiple memory chips of the stack of memory chips are divided into fractions, and multiple internal channels within the package that emanate from the logic chip are coupled to respective ones of the fractions. The logic chip has a multiplexer, including a multiplexer to multiplex a single input/output (I/O) channel of the package to the multiple internal channels.

Stacked memory chip solution with reduced package inputs/outputs (I/Os)

A method is described. The method includes a buffer semiconductor chip receiving a plurality of data signals. The method includes the buffer chip calculating first CRC information from the plurality of data signals. The method includes the buffer chip transmitting the plurality of data signals in parallel with the first CRC information if a read burst transfer sequence is being performed, the buffer chip receiving second CRC information in parallel with the plurality of data signals and comparing the first CRC information with the second CRC information if a write burst transfer sequence is being performed.

Buffer that supports burst transfers having parallel CRC and data transmissions

A method, apparatus and system. The method includes: performing one or more training iterations to tune a target clock signal frequency to be applied at a memory device, each of the one or more training iterations including: causing a modified clock signal frequency to be applied at the memory device; and decoding a quality feedback message from the memory device including an indication of a performance of the clock signal frequency at the memory device; and in response to a determination that the performance of the clock signal frequency falls within a target performance range of the memory device and that the clock signal frequency is below the target clock signal frequency, performing a subsequent training iteration of the one or more training iterations, and otherwise causing application at the memory device, during a memory operation, of a highest clock signal frequency corresponding to a training iteration for which performance of the clock signal was within the target performance range.

Apparatus, system and method to detect and improve an input clock performance of a memory device

Techniques to couple a high bandwidth memory device on a silicon substrate and a package substrate are disclosed. Examples include selectively activating input/out (I/O) or command and address (CA) contacts on a bottom side of a logic layer for the high bandwidth device based on a mode of operation. The I/O and CA contacts are for accessing one or more memory devices include in the high bandwidth memory device via one or more data channels.

Techniques to couple high bandwidth memory device on silicon substrate and package substrate

Examples described herein relate to a pattern of pins where the signals assigned to the pins are arranged in a manner to reduce cross-talk. In some examples, a socket substrate includes a first group of pins that includes a first group of data (DQ) pins separated by at least two Voltage Source Supply (VSS) pins from a second group of DQ pins and a third group of DQ pins separated by at least two VSS pins from a fourth group of DQ pins. In some examples, data strobe signal (DQS) pins are positioned in a column between the first and third groups of DQ pins and the second and fourth groups of DQ pins. In some examples, a second group of pins includes a first group of DQ pins separated by at least two VSS pins from a second group of DQ pins and a third group of DQ pins separated by at least two VSS pins from a fourth group of DQ pins. In some examples, the second group of pins, DQS pins are positioned between the first and third groups of DQ pins and the second and fourth groups of DQ pins.

Package pin pattern for device-to-device connection

Embodiments herein relate to systems, apparatuses, or processes directed to facilitating increased clock speeds on a substrate by lowering the impedance of traces that provide clock signals to components such as DRAM. For example, embodiments may include a substrate with a first layer and a second layer parallel to the first layer with a first trace coupled with the first layer in a routing configuration and a second trace coupled with the second layer in the routing configuration, where the routing configuration of the first trace and the second trace substantially overlap each other with respect to an axis perpendicular to the first layer and the second layer, and where the first trace and the second trace are electrically coupled by a first and a second electrical coupling perpendicular to the first layer and the second layer.

Electrically coupled trace routing configuration in multiple layers

Embodiments disclosed herein include electronic packages and methods of forming such packages. In an embodiment, the electronic package comprises a package substrate, that comprises a bumpout region on a first surface of the package substrate, and a pin region on a second surface of the package substrate. In an embodiment, a data path from the bumpout region to the pin region is included in the electronic package. In an embodiment, a ground path brackets the data path from the bumpout region to the pin region.

Integrated memory coplanar transmission line package having ground path that brackets data path to extend memory speeds

A memory subsystem triggers entry and exit of a memory device from low power mode with a chip select (CS) signal line. For a system where the command bus has no clock enable (CKE) signal line, the system can trigger low power modes with CS instead of CKE. The low power mode can include a powerdown state. The low power mode can include a self-refresh state. The memory device includes an interface to the command bus, and receives a CS signal combined with command encoding on the command bus to trigger a low power mode state change. The memory device can be configured to monitor the CS signal and selected other command signals while in low power mode. The system can send an ODT trigger while the memory device is in low power mode, even without a dedicated ODT signal line.

Applying chip select for memory device identification and power management control

An apparatus is described. The apparatus includes a semiconductor chip having cross-talk noise cancellation circuitry disposed between a disturber trace and a trace to be protected from cross-talk noise emanating from the disturber trace. The trace is to be coupled to a receiver disposed on a different semiconductor chip.

Discrete circuit having cross-talk noise cancellation circuitry and method thereof

A method is described. The method includes configuring first register space to establish ODT values of a data strobe signal trace of a DDR data bus. The method also includes configuring second register space to establish ODT values of a data signal trace of the DDR data bus. The ODT values for the data strobe signal trace are different than the ODT values for the data signal trace. The ODT values for the data strobe signal do not change when consecutive write operations of the DDR bus write to different ranks of a same DIMM.

DDR memory bus with a reduced data strobe signal preamble timespan

Embodiments may relate to a connector. The connector may include a plurality of connector pins that are to communicatively couple an element of a printed circuit board (PCB) with an element of an electronic device when the element of the PCB and the element of the electronic device are coupled with the connector. The connector may also include an active circuit that is communicatively coupled with a pin of the plurality of pins. The active circuit may be configured to match an impedance of the element of the PCB with an impedance of the element of the electronic device. Other embodiments may be described or claimed.

Connector with active circuit

Growing community of inventors

Portland, OR, United States of America

James A McCall