Other

Vlsi Technology, Inc.

Sgs-thomson Microelectronics Limited

Beck Semiconductor LLC

National Semiconductor Corporation

Philips Semiconductors Inc.

M&m Supply Co.

Fail Safe Safety Systems, Inc.

Koninklijke Philips Corporation N.v.

Philips Semiconductor, Inc.

James A Cunningham

Brent H McKnight

Devereux J McKnight

Richard A Blanchard

Vern McKenny

Frank R Bryant

Abha Rani Singh

Carl Greenfield

Anthony M Tuxford

Theordore Kahn

A method for making an integrated circuit device includes forming at least one interconnect structure adjacent a substrate by forming at least one barrier layer, forming a doped copper seed layer on the at least one barrier layer, and forming a copper layer on the doped copper seed layer. The method may further include annealing the integrated circuit device after forming the copper layer to diffuse the dopant from the doped copper seed layer into grain boundaries of the copper layer. The doped copper seed layer may include at least one of calcium, cadmium, zinc, neodymium, tellurium, and ytterbium as a dopant to provide the enhanced electromigration resistance. Forming the copper layer may comprise plating the copper layer. In addition, forming the copper layer may comprise forming the copper layer to include at least one of calcium, cadmium, zinc, neodymium, tellurium, and ytterbium as a dopant. In some embodiments, the dopant in the seed layer may be sufficient so that no additional dopant is needed in the copper layer.

Method for making integrated circuit including interconnects with enhanced electromigration resistance using doped seed layer and integrated circuits produced thereby

An integrated circuit (IC) may include a substrate, a first dielectric layer adjacent the substrate, and at least one trench in the first dielectric layer. The IC may also include a metal liner within the at least one trench, and a first conductive region including copper within the at least one trench. A cap layer including metal may be provided on the first conductive region. A second dielectric layer may be over the first conductive region and the cap layer. A dielectric etch stop and diffusion barrier layer may be over the second dielectric layer, and a via may be over the first conductive region and through the second dielectric layer and the cap layer. A diffusion barrier layer may be on sidewalls of the via, and an alloy seed layer including copper and at least one of tantalum, molybdenum, chromium, and tungsten may be over the diffusion barrier. The alloy seed layer may also be over the dielectric etch stop and diffusion barrier layer, and the alloy seed layer may be in contact with the first conductive region.

Methods of manufacturing copper interconnect systems

Copper interconnect systems

Copper interconnect systems which use conductive, metal-based cap layers

A method for making an integrated circuit device includes forming at least one interconnect structure adjacent a semiconductor substrate and including a copper portion and at least one barrier layer adjacent to the copper portion, and displacement plating surface portions of the copper portion with a plating metal more noble than copper and different than copper. The method including displacement plating provides selective and self-limiting thickness plating and enhances the electromigration resistance of the interconnect structure. The displacement plating may include subjecting the copper portion to a plating bath including the plating metal. Because displacement plating is used and is not an electroless plating process, the concentration of the metal in the aqueous plating bath and the plating time are not critical. The method may further include annealing the integrated circuit device after the displacement plating to diffuse the plating metal into the copper portion. The plating metal may comprise at least one of silver, gold, mercury, rhodium, palladium, iridium, and platinum.

Method for making integrated circuit including interconnects with enhanced electromigration resistance

A locked connection comprises a circular groove around a pin or inside member. A box or outside member provides a series of passages tangential to the groove in a made up position of the box and pin. One or more locking pins extend through the passages. When the box and pin tend to move relative to each other, the locking pin is placed in shear in a path extending along the long dimension of the pin whereby a large shear area is provided by a small diameter locking pin.

Locked connection

An improved gate electrode provides greater tolerances to higher temperature annealing treatments, and is useful in connection with the formation of self-aligned contacts as are needed for high density embedded DRAM applications. Consistent with one embodiment, a process for manufacturing a polycide transistor gate electrode involves forming a cap dielectric and dielectric spacer, with the electrode exhibiting a reduced diffusion transport of dopants between an underlying doped polysilicon layer and an overlying suicide layer. The reduced transport results from the presence of a thin barrier layer between the doped polysilicon layer and silicide layer, and the gate electrode process forms a thermally-oxidized thin polysilicon side-wall film against the polysilicon layer, the barrier layer, the silicide layer, and the cap dielectric layer. The polysilicon side-wall film is used for blocking substantial oxidation of the barrier film.

Semiconductor device with high-temperature-stable gate electrode for sub-micron applications and fabrication thereof

For downwardly-scaled semiconductor processing, high-conductivity metal diffusion is blocked using extremely thin barrier films/layers. Diffusion of a highly-conductive metal is minimized using a dielectric barrier layer positioned a distance under the high-conductivity metal and a distance above the active regions of a semiconductor device. According to one embodiment, a semiconductor device also includes a highly-conductive metal interconnect patterned over a conductive partial diffusion barrier and adhesion promoting film. An underlying dielectric barrier layer against diffusion of the metal interconnect is formed above the active area but not in direct contact with the metal interconnect and is used to block diffusion that is not blocked by the partial diffusion barrier and adhesion promoting film. In a more specific embodiment, the metal interconnect is coated on the upper surface and edges with a thin electrolessly deposited partial barrier film, such as nickel or cobalt.

Arrangement and method for improved downward scaling of higher conductivity metal-based interconnects

An integrated circuit includes a substrate, at least one dielectric layer adjacent the substrate, and an interconnect structure in the at least one dielectric layer and comprising a copper portion and a barrier layer between the copper portion and adjacent portions of the at least one dielectric layer. Moreover, the barrier layer preferably comprises at least one of rhodium, ruthenium and rhenium. These materials are virtually insoluble and immiscible in copper, and can be readily deposited by electroless deposition, for example. The barrier layer may be in contact with the adjacent portions of the at least one dielectric layer. In addition, at least one other barrier layer can be provided between the barrier layer and the copper portion. The interconnect structure in some embodiments may extend both laterally and vertically within the at least one dielectric layer.

Diffusion barriers for copper interconnect systems

Exemplary embodiments are directed to providing a flash EEPROM technology which is compatible with deep submicron dimensions, and which is suitable for straightforward integration with high performance logic technologies. Unlike known technologies, exemplary embodiments provide a reduced cell area size in a split gate cell structure. An exemplary process for implementing a flash EEPROM in accordance with the present invention involves growing a tunneling oxide in a manner which reduces tunneling barrier height, and requires minimum perturabition to conventional high performance logic technologies, without compromising logic function performance.

Method of fabricating Nan embedded flash EEPROM with a tunnel oxide grown on a textured substrate

A valve includes a valve ball and a convex metal valve seat ring that abut along a circle in a metal-to-metal seal. At very high contact forces, the valve ball and/or the valve seat elastically deform to increase the contact area between them and thereby lower the contact pressures applied to the valve ball and valve seat. The valve ball and valve seat are made of materials that do not pressure weld under a wide range of contact pressures. In one embodiment, the valve ball is a stainless steel alloy having a hardness of at least Rockwell 44C and the valve seat is Stellite having a hardness of at least Rockwell 50C. In another embodiment, the valve ball and seat ring are steel alloys having hardnesses above Rockwell 50C.

Growing community of inventors

Saratoga, CA, United States of America

James A Cunningham