Samsung Electronics Co., Ltd.

Jai-Hoon Sim

Kyu-Chan Lee

Ki-Nam Kim

Won-Suk Yang

Jae-Kyu Lee

Sang-bo Lee

Jae-Gyu Lee

A method for fabricating a semiconductor device with different gate oxide layers. Oxidation is controlled in accordance with the active area dimension so that oxide grows thin at a wider active width (peripheral region) and grows thickly at a narrower active width (cell array region). A gate pattern is formed on a semiconductor substrate having different active areas. Gate spacers are formed and then active dimension dependent oxidation process is performed to grow the oxide layers differently from one another.

Method for fabricating a semiconductor device having different gate oxide layers

Narrow-channel effect free DRAM cell transistor structure for submicron isolation pitch DRAMs having lowed-doped substrate and active width-independent threshold voltage by employing conductive shield in the shallow trench isolation(STI). The resulting cell transistor structure is highly immune to parasitic E-field penetration from the gate and neighbouring storage node junctions via STI and will be very appropriate for Gbit scale DRAM technology. The conductive shield is biased with the negative voltage in order to minimize the sidewall depletion in the substrate.

Methods of forming trench isolation regions having conductive shields

Driving circuits with active body pull-capability for inhibiting boost delay include main, subordinate and boosted signal lines and a first driver circuit electrically coupled to the main signal line, to drive the main signal line at a first potential (e.g., Vcc). A second driver circuit, electrically coupled to the boosted signal line, is also provided to drive the boosted signal line at a second potential (e.g., Vpp) greater than the first potential. A first field effect transistor is provided as a pull-up transistor which has a gate, drain and source electrically coupled to the main signal line, the boosted signal line and the subordinate signal line, respectively. To reduce body-bias effects which might inhibit the speed and pull-up capability of the pull-up transistor, a second field effect transistor is provided to actively pull-up the body (e.g., active region) of the pull-up transistor. This second field effect has a gate, drain and source electrically coupled to the main signal line (or boosted signal line), the boosted signal line and the body of the pull-up transistor, respectively. The second field effect transistor is designed to provide a pull-up function to the body of the pull-up transistor so that the magnitude of the reverse bias between an inversion layer channel (e.g., N-type) and the body region (e.g., P-type) of the pull-up transistor is reduced when the pull-up transistor is turned on to provide a voltage boost to the subordinate signal line. This reduction in the reverse bias results in a reduction of the body-bias effect and the increase in threshold voltage typically associated with the body-bias effect.

Signal line driving circuits with active body pull-up capability for

A reference voltage generator includes a pull-up stage which pulls a reference voltage signal rapidly up toward 1/2Vcc at power-up. The pull-up stage is controlled by a controller which has a comparator and control voltage generator which are disabled after the pull-up operation is terminated so as to reduce stand-by current consumption. The controller includes a pair of NAND gates cross connected as an RS flip-flop to turn on the pull-up stage at power up. A boost signal allows the flip-flop to enable the comparator and control voltage generator after the power supply has stabilized. When the reference voltage signal reaches 1/2Vcc, the comparator sets the flip flop which turns off the pull-up stage and disables the comparator and control voltage generator.

Reference voltage generator with fast start-up and low stand-by power

Integrated circuit memory devices include at least first and second memory cells electrically coupled to respective first and second sense bit signal lines of a sense amplifier. The sense amplifier comprises a circuit for amplifying a difference in potential between the first and second sense bit signal lines by driving these lines to respective first and second different potentials. A driving circuit is also provided for simultaneously driving the first and second sense bit signal lines towards the first potential in response to application of a boost control signal. This driving circuit preferably comprises a first capacitor electrically connected in series between the boost control input and the first sense bit signal line and a second capacitor electrically connected in series between the boost control input and the second sense bit signal line. The boost control signal is established at the first potential to drive both the sense bit signal lines from different intermediate potentials (e.g., 1/2VCC+, 1/2VCC) towards the first potential, prior to amplification of the difference in potential between the first and second sense bit signal lines by the sense amplifier. The present invention enables the sense amplifier to operate in an environment where the power supply voltage (e.g., VCC) is reduced and the different intermediate potentials (e.g., 1/2VCC+, 1/2VCC) to be amplified are initially established at potentials below the normal sensitivity of the sense amplifier.

Sense amplifier for integrated circuit memory devices having boosted

A voltage driving circuit for use in a semiconductor memory device. The voltage driving circuit includes a generator which generates a first voltage for an operating mode of the device, a generator which generates a second voltage for a standby mode, and a pair of switches connected between the voltage generators and an operating circuit, for selectively supplying the first and second voltages thereto. The first and second switches each have a control terminal, both of which are commonly coupled to a mode signal, for allowing external control of the voltage selection. The first and second voltages are preferably set relative to each other so as to reduce the subthreshold leakage current consumed by the semiconductor memory during a standby mode, while maintaining a desired operating speed during an operating mode.

Mode-selectable voltage driving circuit for use in semiconductor memory

A current sense amplifier for use in a semiconductor memory device having a pair of sub-I/O lines and a pair of I/O lines includes a first circuit leg having a first PMOS transistor in series with a second NMOS transistor. A second circuit leg has a third PMOS transistor in series with a fourth NMOS transistor. The gates of the PMOS transistors are each cross coupled to the drain of the other PMOS transistor. The gates of the NMOS transistor are each cross coupled to the source of the PMOS transistor in the other circuit leg. The source of each PMOS transistor comprises a sub-Input/Output line with an Input/Output line located between the transistors in each of the legs.

Current sense amplifier for use in a semiconductor memory device

A current sense amplifier circuit for a semiconductor memory device includes a differential amplifier which senses the signal currents input to first and second input nodes, amplifies the difference between the two signals and outputs the sense-amplified signals to first and second output nodes. A first feedback circuit is connected between the second input node and a current controlling node and has a controlling terminal connected to the first output node. A second feedback circuit is connected between the first input node and the current controlling node and has a controlling terminal connected to the second output node. By feeding back voltages from the counterpart output nodes through the cross-connected feedback circuits, the difference between low level input signals can be efficiently detected and a stable sense-amplified output is obtained.

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Kyungki-do, South Korea

Jai-Hoon Sim