Intel Corporation

Micron Technology Incorporated

Sony Semiconductor Solutions Corporation

Jahanshir J Javanifard

Kerry Dean Tedrow

Mase J Taub

Daniele Vimercati

Richard Edward Fackenthal

Hari Giduturi

Rodney R Rozman

Jeffrey J Evertt

Angelo Visconti

Gregory E Atwood

Jerry A Kreifels

Jeffrey J Peterson

Christopher John Haid

Jeff Evertt

Jin-lien Lin

Rajesh Sundaram

Duane R Mills

Robert E Larsen

Vishram P Dalvi

Cesar Galindo

Joseph W Tsang

Albert Fazio

James Brennan, Jr

Marc E Landgraf

Priya Walimbe

Makoto Kitagawa

Raymond W Zeng

Hing Yan To

Sanjay S Talreja

Richard Keith Dodge

Sherif R Sweha

Sachidanandan Sambandan

Brian G Johnson

Mark D Winston

Kevin W Frary

Mathew B Nazareth

Steve Wells

Muneer Ahmed

Balasubramanian Venkataraman

Michelle Y Eng

Tom H Ly

Duane F Mills

Kimberley D Meister

Vishram Prakash Dalvi

Dave Ward

Methods, systems, and devices for data masking for memory are described. A memory device may set multiple data masking flags for associated memory array(s) at power-up. Each data masking flag may be associated with a respective page of memory cells and may indicate whether the data stored in the respective page is masked data, or whether the data is new, unmasked data. Data existing at a previous power-down may be masked until an initial write or activate command has been performed on the page after power-up, where the initial write or activate command may result in writing masked data, write data, or a combination thereof to the page. After previously stored data is overwritten to a page, the flag associated with the page may be reset, which may indicate that data stored at the page is available to be read.

Data masking for memory

Methods, systems, and devices for cell data bulk reset are described. In some examples, a write pulse may be applied to one or more memory cells based on an associated memory device transitioning power states. To apply the wire pulse, a first subset of digit lines may be driven to a first voltage and a plate may be driven to a second voltage or a third voltage. While the digit lines and plate are driven to the respective voltages, one or more word lines may be driven to the second voltage or the third voltage. In some instances, the digit lines may be selected (e.g., driven) according to a pattern.

Cell disturb on power state transition

Methods, systems, and devices for cell data bulk reset are described. In some examples, a logic state (e.g., a first logic state) may be written to one or more memory cells based on an associated memory device transitioning power states. To write the first logic state to the memory cells, a first subset of digit lines may be driven to a first voltage and a plate may be driven to a second voltage. While the digit lines and plate are driven to the respective voltages, one or more word lines may be driven to the second voltage. In some instances, the word lines may be driven to the second voltage based on charge sharing occurring between adjacent word lines.

Memory system configured to perform a reset on one or more non-volatile memory cells upon transitioning power states

Methods, systems, and devices for speculative memory section selection are described. Defective memory components in one memory section may be repaired using repair components in another memory section. Speculative selection of memory sections may be enabled, whereby access lines in multiple memory sections may be selected when a memory command indicating an address in one memory section is received. While the access lines in the multiple memory sections are selected, a determination of whether repair components in another memory section are to be accessed is performed. Based on the determination, the access line in one of the memory sections may be maintained and the access lines in the other memory sections may be deselected.

Speculative section selection within a memory device

Methods, systems, and devices for section-based data protection in a memory device are described. In one example, a memory device may include a set memory sections each having memory cells configured to be selectively coupled with access lines of the respective memory section. A method of operating the memory device may include selecting at least one of the sections for a voltage adjustment operation based on a determined value of a timer, and performing the voltage adjustment operation on the selected section by activating each of a plurality of word lines of the selected section. The voltage adjustment operation may include applying an equal voltage to opposite terminals of the memory cells, which may allow built-up charge, such as leakage charge accumulating from access operations of the selected memory section, to dissipate from the memory cells of the selected section.

Access schemes for section-based data protection in a memory device

A memory device comprising a plurality of memory tiles, each tile comprising a local common source line (CSL) plate, a plurality of bitlines and a plurality of wordlines, each coupled to a plurality of memory cells and a masking circuit, coupled to each of the memory tiles, for controlling whether to raise the local CSL plate and the plurality of bitlines based on the a global common source line.

Memory device with a common source line masking circuit

A Phase-Change Memory (PCM) having a temperature detector with a dedicated PCM bit programmed to an amorphous state and a circuit to determine that the dedicated PCM bit is no longer in the amorphous state. A temperature exposure signal is asserted to indicate that a high temperature has altered PCM device programming integrity.

Phase-change memory temperature sensitive detector

A flash memory device including a first memory array, a control circuit coupled to the first memory array, and a second independent memory array coupled to the control circuit. The first memory array includes a plurality of memory blocks each having a memory cell. The memory cell may be a nonvolatile flash memory cell. The control circuit controls the programming, erasing, and reading of the memory cells. The second memory array includes a plurality of block lock-bits each corresponding to one of the plurality of memory blocks. The state of each block lock-bit indicates whether the memory cell in the corresponding memory block is locked. The second memory array may also include a master lock-bit that indicates whether the block lock-bits are locked.

Block locking apparatus for flash memory

A programmable current source for a phase change memory allows a single current source to controllably provide the current for reading and writing both set and reset bits. In addition, the current source can vary the current based on the characteristics of a particular run of wafers. In one embodiment, a plurality of current generators may be selectively operated to generate the desired additive output current that is needed for a particular operation such as reading or writing set or reset bits.

Providing current for phase change memories

In one embodiment, the present invention includes a method to supply a negative voltage to at least one deselected wordline of a memory array. Further, while the negative voltage is supplied to deselected wordlines, a positive voltage may be supplied to a selected wordline. The memory array may be a flash memory incorporating multi-level cell architecture, in one embodiment.

Negatively biasing deselected memory cells

A DC voltage boost circuit including a regulation circuit that produces a pulse width modulated control signal for regulating the output of the DC voltage boost circuit. Various embodiments of regulation circuits are disclosed. In one embodiment, the regulation circuit includes a waveform generator for generating a triangular waveform and a comparator for producing the pulse width modulated control signal by comparing the triangular waveform with a voltage that varies proportional to the booster output voltage. In another embodiment, the regulation circuit includes a waveform generator for generating a sawtooth waveform whose rise time varies inversely with the booster output voltage and a comparator for producing the pulse width modulated control signal by comparing the modulated sawtooth waveform with a substantially constant voltage. Yet, in another embodiment, the regulation circuit includes a counter for generating a count that sequentially cycles in response to a clock signal, wherein the counter is reset in response to a change in the booster output voltage, and a logic circuit for generating the pulse width modulated control signal from the count.

Regulator design for inductive booster pump using pulse width modulation technique

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Sacramento, CA, United States of America

Jahanshir J Javanifard