Intel Corporation

Jagir S Multani

Xiao-Chun Mu

John T Orton

John K Chu

Sanjiv K Mittal

Robert Jecmen

An etchback process for etching a refractory metal layer formed on a semiconductor substrate with a greatly reduced micro-loading effect. The etch proceeds in three steps. The first step is a uniform etch which utilizes a gas chemistry of SF.sub.6, O.sub.2 and He and proceeds for a predetermined time to remove most of the metal layer. The second step is a very uniform etch which utilizes a gas chemistry of SF.sub.6, Cl.sub.2 and He and proceeds until the endpoint is detected. The endpoint is detected by measurement and integration of the 772 nm and 775 nm lines of Cl. The third step is a timed etch utilizing a gas chemistry of Cl.sub.2 and He which is used as both an overetch to ensure complete removal of the refractory metal film and as a selective etchant to remove an adhesion underlayer.

Etchback process for tungsten contact/via filling

Novel etch back process for tungsten contact/via filling

Plasma etching process for refractory metal vias

A planarization process for a double metal very large scale integration (VLSI) technology is disclosed. To compensate for an irregular surface topology encountered in a dielectric medium between the two metals, a CVD dielectric layer and a glass layer are first deposited above the first metal. Then an etch-back process is used to uniformly etch back the CVD dielectric and the glass layers at the same rate, leaving a planarized surface for subsequent deposition of a second dielectric layer and a second metal layer.

Surface planarization method for VLSI technology

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Fremont, CA, United States of America

Jagir S Multani