Samsung Electronics Co., Ltd.

Snu Rdb Foundation

Jaeyong Jeong

Kitae Park

Sang-Wan Nam

Jinwoo Park

Hyun-Wook Wook Park

Won-Taeck Jung

Jinwoo Kim

Byungsoo Kim

Wandong Kim

Ju Seok Lee

Beomkyu Shin

Wontaeck Jung

Kuihan Ko

Kuiyon Mun

Bohchang Kim

Kyung Ho Kim

Youngwook Kim

Sangkwon Moon

Jihong Kim

Myung Hyun Jo

Seung-Bum Kim

Sangyong Yoon

Sang-Hyun Joo

Sang-Soo Park

Jungho Park

Dongkyo Shim

Myung-Hoon Choi

Jung-Soo Kim

Ohsuk Kwon

Hyun Jun Yoon

Wonhee Cho

Hyunjun Yoon

Youngsun Song

Insu Kim

Myunghyun Jo

A memory system includes a first memory device including a plurality of first memory blocks each including a plurality of first memory cells stacked in a direction perpendicular to a substrate; and a memory controller configured to control a memory operation of the first memory device. The memory controller is configured to select and operate any one of different control schemes for each of the first memory blocks based on a number of first not-open (N/O) strings included in each of the first memory blocks, respectively.

Memory device, memory controller, and memory system including the same

A non-volatile memory device is provided. The non-volatile memory device includes a clock pin, a clock signal being received from a controller through the clock pin; a first input/output pin; a second input/output pin, data being received from the controller in synchronization with the clock signal through the second input/output pin; a command/address buffer configured to operate at a first operating speed and buffer a command and an address received through the first input/output pin in synchronization with the clock signal; a memory cell array including a plurality of memory cells; and a control logic configured to control operations with respect to the plurality of memory cells, based on the command and the address buffered in the command/address buffer.

Non-volatile memory device, controller and memory system

A memory device including: a memory cell array including a plurality of memory cells forming a plurality of strings in a vertical direction with a substrate; and a control logic configured to detect a not-open string (N/O string) from the plurality of strings in response to a write command and convert pieces of target data to be programmed on a plurality of target memory cells in the N/O string so that the pieces of target data have a value that limits a number of times a program voltage is applied to the plurality of target memory cells.

Method of detecting a not-open string (N/O string), converting target data, with a value that matches inhibit data, to be programmed to target memory cells in the N/O string, and programming the memory cells

A three-dimensional (3D) nonvolatile memory device includes a cell string. The cell string includes a pillar structure comprising a ground selection transistor, a plurality of memory cells, and a string selection transistor stacked vertically over a substrate. The memory cells comprise a first cell group and a second cell group stacked on the first cell group, and a horizontal width of at least a portion of the pillar structure decreases in a depth direction towards the substrate. A method of programming the memory device includes initializing a channel of a memory cell of the first cell group of the cell string through the ground selection transistor of the pillar structure, and then applying a program voltage to the memory cell of the pillar structure of the cell string.

Non-volatile memory device and memory system including the same and program method thereof

A non-volatile memory device includes a memory cell array including memory cells respectively connected to bit lines; and a control logic unit configured to control a program operation with respect to the memory cells. The control logic unit is configured to perform a normal program verify operation with respect to the memory cells by using a normal program verify condition, during the program operation, and, based on a suspend command that is received during the program operation, perform an initial program verify operation with respect to the memory cells by using an initial program verify condition that is different from the normal program verify condition.

Non-volatile memory device and programming method thereof

An operation method of a storage device including first and second physical functions respectively corresponding to first and second hosts includes receiving performance information from each of the first and second hosts, setting a first weight value corresponding to the first physical function and a second weight value corresponding to the second physical function, based on the received performance information, selecting one of a first submission queue, a second submission queue, a third submission queue, and a fourth submission queue based on an aggregated value table, the first and second submission queues being managed by the first host and the third and fourth submission queues are managed by the second host, processing a command from the selected submission queue, and updating the aggregated value table based on a weight value corresponding to the processed command from among the first and second weights and input/output (I/O) information of the processed command.

Storage device for supporting multiple hosts and operation method thereof

A system-on-chip includes a first intellectual property (IP) generating a plurality of request packets; and a second IP generating a plurality of response packets based on the plurality of request packets, wherein the second IP includes a plurality of processing elements processing the plurality of request packets and generating the plurality of response packets; a distributer, when the plurality of request packets are input from the first IP, determining a scheduling policy based on a packet type of the plurality of request packets and distributing the plurality of request packets to the plurality of processing elements according to the determined scheduling policy; and an aggregator, when the plurality of response packets are received from each of the plurality of processing elements, aggregating the plurality of response packets according to the determined scheduling policy.

Integrated circuit device, system-on-chip including the same, and packet processing method

Growing community of inventors

Yongin-si, South Korea

Jaeyong Jeong